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I see nothing special when i look at the datasheet of 16c711 except that it has a 4 channel 8 bit adc which neither 16f628 nor 16f84 has. If your application does not need the adc either 16f628 (2K codespace) or 16f84 (1K codespace) should be able to replace your 16f711. Maybe you can post the project here so that we can take a look at (...)
Hi all I'm trying to simulate a coax cable to lear how to use the tool. Neither help nor the tutorials coming with the bundle helped me to understand what is going on exactly..... :-( I understood the "terminal lines" though. 1) What's the purpose of an "impedance line" and how do i use it? 2) same question for "calibration line". T
Hi, I would like to use a graphical lcd in my project but i can not simulate a PG160128A lcd with proteus.Neither example files of CCS nor source codes for glcd which i collected here, works So, if anyone can simulate this glcd, please send ccs codes and proteus file to me to I will be appreciated if som
C to VERILOG .. no way ! i'm sorry to be brutal !.. but HANDEL-C is not an easy C . nor is verilog . The reason is C is a SEQUENTIAL language .but VHDL,verilog are parellel languages .though the language has a lot of similarities ,there are less than there are more similarities .Defining wires variables .. and other critters is only 10 % of the
Hi This code is not tested nor simulated. Check the syntax and simulate it. It could be a starting point for your work. entity Interrupt_controller is port ( CLK_IN : in std_logic; -- Clock input CS_IN : in std_logic; -- External Chip Select input IN_0 : in std_logic; -- First Irq source input IN_1 : in std_logic; -- Second Irq
After synthesis and optimization of my verilog file, I find some net( or wire) names is very strange. For example , the net connected from the output of nor gate to the data input of D flip-flop is called " *cell*11/U2/control ". But I want very short net name like " N100" . Does anyone know the answer to this question ? Cyteng