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246 Threads found on edaboard.com: Nor Not
Hello everyone, I would like to know about VS motor. This type of variable speed motor is not a combination of VFD with induction motor nor it is a DC motor with speed controller. Perhaps it is an induction motor but different approach in speed control. I only heard the description of it. Also I tried with few books and could not find any (...)
Hi, I write a custom library for synopsys design vision which only consists of XOR, nor, and IV (inverter or not). My plan is to synthesize a combinational logic such that the resulting netlist has minimum number of nor gates. I write the library as flows: library(and_or_xor) { cell(nor) { area : 1000; (...)
I would expect process value and setpoints represented by simple signed or unsigned integers, neither arrays nor character strings. In case that the setpoint is given as a decimal string, it would be converted to an integer number, e.g by atoi() before comparing it with the process value. this definition gives an error with GNU C
For the same drive strength, the NAND-not combination needs less silicon space than the nor solution. Vice versa, by using your nor solution on the same silicon area as the NAND-not combination, the nor output has less drive strength. However, if you don't mind about drive strength (or silicon area (...)
Dear norbila Md nor. You can use these pdf files. I wish this helps!
do you need to vary the voltage and have a current limit? - - - Updated - - - you can design a BUCK converter in order to get this voltage , because it will be more efficient than a linear converter. though that is often true it is not the only consideration, nor maybe not th
here for almost all current mcu today but you did not specify your mcu, nor the language you use ?
Energy by default flows from source to sink. Only at RF we consider reflected power and measure it. It is not the case at DC nor mains AC. Maybe rikotech8 is asking about measuring energy flow in power grid where exists more than one energy source? Who knows?
I don't see neither eq. 4.49 nor 4.48
Hello, How could you make layout XL "focus" only on the layout and not some extra space around the layout ? The thing is that when i generate my cell, it creates a larger cell than it should be because of an "extra" space added i don't know why ! There is no floating pin nor any other object, still it confuses me. Thanks for your help[A
You get something wrong here.... To get 'perfect reconstruction signal' you need to sample it with as least twice its band frequency. Halfband filters are special group of FIR filters that got passband frequency equall to 0.5 of they normalized frequency
You think a simulation testbench is going to tell you about anything but "ideal" accuracy? It's quite likely that, outside places like AD, LTC, TI, your diodes are not modeled well enough for sub-% bandgap or temp sensor accuracy - neither nominal nor process-varying, and maybe even temperature is not credible. Certainly a "non-valued" diode (...)
On schematics at my job, they use circles on the inputs of gates , what are the names for these types of negative logic gates? They aren't called AND, OR, NAND, nor, Exclusive OR or nor, they have different names , what are they called? When would a circuit or in general want to use Negative Logic gates? The Negative logic gates have inte
nor GATE U10 only works when the input voltage was comparing Positive voltages, it didn't work when comparing Negative voltages, why? I changed it and it works now 99922 99923 99924 What type of RC network is that , what does the Diode do? it discharges the cap?
You would use "bit wise" operators such as not, AND, OR, NAND, nor, and XOR. For example, if each array element was 16 bits, first mask off the LSB using AND with 1111111111111110 and then use OR with 000000000000000x on the result. x is the new LSB value. I assume when you say LSB of the array you mean the LSB of each element of the array. The key
I have a transmission gate flip flop with nor gates for set/reset . In simulation, this flipflop works fine at high frequencies ~10MHz but when I clock it at 100 kHz, it starts to fall apart. Does transmission gate FF not work for frequencies below 100 kHz?? I'm using 90 nm cmos.
Are you sure that you are talking about control of digital inputs, 1A can't be handled by a microcontroller pin nor a 74HCxxx chip, you can use a discrete mosfet or smart switch
I suppose that's not the correct architecture body, can't imagine that your synthesis tool or simulator accepts it. Referring to the original post, I don't see the said one bit "flip-mux" component, nor respective component instantiation statements. I guess you better to start reading a VHDL text book.
I'm not really a good C programmer, nor am I familiar with the DSPIC3, but where is your output to the LED in your code? Are you mapping the timer output to a pin? Where do you assign your port directions?
whether the above conditions are synthesizable You're on the right track. Neither x nor z are synthesizable as input values. That's why the discussion is almost meaningless for synthesized code. It's mainly a question of possible simulation mismatch.