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# Nor Not

246 Threads found on edaboard.com: Nor Not

## How to determine if the system is an LTI System, if we are given H(jw)?

How to determine if the system is an LTI System, if we are given H(jw)? If we are not given with the input x(t) nor output y(t), is it still possible to determine if the system is LTI or not? If we are given input x(t) and y(t), how should we determine if the system is LTI or not? How do you know if the information (...)

## Error Line 135: found '0' definitions of operator "+", cannot determine exact.......

Real type is neither synthesizable nor defined in numeric_std.

## Parallel NOR flash power supply design

Dear Sir, I want to calculate the power requirement of an nor flash from micron. IC requires two power supplies: VCC(core) & VCCQ(I/O). I calculated the power requirement of VCC(core) from the data sheet as VCC(max) * ICCW. I want to calculate the power requirement of the VCCQ(I/O) supply. I am not able to get the data from the ven

## Ideas for final year project

I have a large scale project in mind for commercial use. A growing trend in lighting is automated control, yet the standards are not yet in place nor what is being done that cost-effective nor encompassing. Interested? PM me for more.

## Problem with ARM microcontroller ethernet controller and DP23848 chip

Since my program works very well in 10Mb mode, I doubt if there is a problem in software or hardware. Of course the real lesson is not falling into this mindset. If the problem exists in neither the software nor hardware, where could it exist? BigDog

## Need Help with Verilog Code for a Dice

I got this project where I got to build the Snakes and Ladders Game. Requirements are CPLD Explorer XC9572XL Xilinx Verilog The joke is through my whole semester the prof. taught us about Kmaps, ICs, Combinational Circuits and so on...the basics the last class he taught us was about Verilog ----- and or xor not nor nand (||,&&,! et

## verilog strength coding

Yes, Verilog does not add drive strengths together, nor does it reduce strengths based on how much fanout the signal has.

## NOR FLASH Controller in vhdl

If you are interfacing nor flash with the Xilinx FPGAs then Xilinx tolls supports this we don't need to write..

## timer0 programing in Atiny461a

i try to program the timer0 module in attiny461a. but...timer value is incrementing but interrupt is nor generated.... i try to simulate this in avr studio but timer value is not incrementing.when i test that same code in hardware with the help of an lcd display i saw the timer value is incrementing... these are my register values TCCR0A=0b

## CMFB for a 2 stage opamp (continuous)

but the first stage was not fixed ......why does this happen By nature of a two-stage amplifier. It's neither feasible nor useful to bias the first stage output to Vdd/2. The bias point of the first stage is commanded by Vth of the second stage transistors.

## Various Electronic Analysis Questions

Image 7 looks like it might be a one-input bistable multivibrator. Two symmetrical nor gate arrangements, which are made to change to the opposite state whenever a pulse comes from the upper left. Pulse-on, pulse-off. Hence image 8 shows two bistable multivibrators. I could be wrong. Diodes might ensure current goes one way and not the other. Or

## Equiv. impedance of a loaded TEM cell: series or parallel?

Hello again! I have computed the S-parameters of a TEM cell and determined the absorbed power as P_abs=P_incident(1-|s11|^2-|s21|^2) The absorbed power determined as such is actually the active power (not the reactive, nor the apparent), isn't it? Then I loaded the cell with some lossy probes and re-computed the S-parameters and again the absorb

## Modelsim Output for System Verilog code

hi all, How to cheak output of this code in Modelsim, I am not getting any output neither in transcript window nor in wave window ,Please explain how to check this code output plz reply the modelsim command to see the output virtual class A ; virtual task disp (); \$display(" This is class A "); endtask endclass class EA extends A

## System verilog code output

hi all, How to cheak output of this code in Modelsim, I am not getting any output neither in transcript window nor in wave window ,Please explain how to check this code output virtual class A ; virtual task disp (); \$display(" This is class A "); endtask end

## how to understand the equation in pic?

X^n represents a sequence, and x^n seems to do the same thing, what is the difference? In the picture you posted there are not any X^n nor x^n. Can you clarify? Z

## costs medical device certification

dear all, I am looking for a estimation of the costs in involved regarding the certification of a medical device. This is device is not invasive nor is it in contact with the skin and it is powered from a single cell Li batt. I am just looking for a global costs estimation. Some estimation or experience sharing would be greatly appriciated

## DC-DC converter urgent help

You have not mentioned your current/power requirement. nor much other parameters, either - such as isolated/not isolated and if not isolated, if the most negative wire in input os "ground" and common to the output, or if you have some more unusual needs. Without more info it is hard to guide you to viable solutions. The (...)

## RTL Logic Gate help - 2x In OR / 3x In XOR

First, I think you need to write out your truth tables, that will help you answer some of your questions. A 3input nor is most definitely not the same as an Xnor (look at your truth tables!) Yes, if you invert the output of a nor you'll have an OR. And vice versa.

## Interfacing AT89C51 with ultrasonic sensor and LCD

not that I'm familiar with the u/sound sensor nor the microcontroller, but where in the code did you insert the wait state until you see a ping response? All I saw was fixed delays, but maybe I missed it in the code. It looks like the code is copied from here, but with the ping

## [MOVED] opamp linearity at higher freqs

... butno clue so far.. nor have I. Just guesswork: 1. Are you sure your input is symmetric? 2. Is the non-linearity already visible at the connections to the cascode followers (M5-M10 & M6-M11)?