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Hi guys, I designed a PLL, and I'm not getting to a locking state yet. I'm trying to debug the problem by observing the behavior of different signals. It seems that I'm getting only Up Pulses and the behavior is periodic. here is one that simulation that shows the periodic behavior of Up pulses: 157210 [ATT
#include #define _XTAL_FREQ 8000000 #include "lcd.h" // CONFIG1H #pragma config OSC = HS // Oscillator Selection bits (HS oscillator) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchove
library ieee; -- line 1 use ieee.std_logic_1164.all; -- line 2 -- line 3 entity find_errors is port( -- line 4 a: in std_logic_vector(0 to 3); -- line 5 b: out std_logic_vector(3
hello friends,pls suggest me best project center in Chennai? i am the final year student..
Maybe I'm missing something, but you seem to have an enormous misunderstanding of, well, everything. The way you describe it, your system inflates a balloon proportional to the AMOUNT with no regard to WHAT the actual data is? Hard drives dont change size. They dont get smaller when you read data. You need to either rethink your idea, or explain it
The phase margin is 72 degree when the gain is 0dB. However, the phase margin is close to 0 before the frequency reaches the unity-gain bandwidth. Is the op-amp stable? Why? Thank you. 157193
I have downloaded BSIM4 from Berkeley website. All the source codes are in C language. Do you know how to start running this source code? How can i use it? Thanks
I have to be able to measure the TOI of a power amplifier. I read on-line that the frequency tone spacing that can be used for this test is 100 MHz with a 1 MHz resolution but this does not apply for amplifiers that don't have that kind of bandwidth. Is there a ROT for determining what the frequencies of the tones should be based on the center fr
Hi, All Gurus, I finally selected ADM6316xxxX, which has a watchdog time from 100ms, from 71ms~153ms. It is acceptable. The outside reset signal will be connected to WDI as following. I still doubt if it can work as my supposed: 1. normally WDI=+3.3V, 2. when want reset, WDI=0V, 2.1 if WDI=0V last more than watchdog time, then output
Assume the probability of Event is a complex number p exp(-i\theta), where |p| is the observed probability. Assume a AND circuit = p1(exp -i\theta1) p2(exp -i\theta2) a not operation = (1-p)(exp -i\omega) a "1" = (1-p)exp( -i \omega) + p exp( i \theta) Yes probabilities all interfere because laws of physics would not even start. Say for e
Hi, I have a question regarding differential negative feedback circuit, addressed in Design of analog CMOS integrated circuits written by Razavi. On page 314 (Figure 9.30 (b)), Each output of an fully differential amplifier is shorted to the input of the amplifier to address the need for CMFB(Common mode feedback). (Resistor load is use
Can simulator like ncverilog simulates the metastability behavior of CDC circuits? How to do simulations with metastability models (RTL and gate-level)?
Why we used derate factor while calculating delay of a path ? and What is the impact of derate factor, if we do not consider at all?
Hi We have pulses which we need to delay by some approx. 280ns, and indeed we need to make the pulses shorter, again by some approx. 280ns The attached (ltspice sim and pdf) show two circuits which could possibly achieve this. Do you agree that the top circuit, which uses a logic buffer IC, is not workable in reality due to the high output impe
I did simulate a microstrip line in a EM solver, and extracted the distributed circuit parameters in a matlab script. With these parameters, I can build a circuit in ADS to which has comparable S-parameters with the EM solver simulation. This gives my linear circuit parameters. Further, I introduced some dielectric materials onto the microstrip
Hi, I am simulating my postgraduate PCB design project using Hyperlynx SI tool. I am testing on PCIe traces of my design. I did my design using Altium and I exported to Hyperlynx file to do the simulation. I have a issue in TX differential pair of the design. It did not pass the simulation. So I need to change the trace width and spacing of the
Hi, I am doing Doherty power amplifier design with 25 Watt power capability using CGH40010F transistors provided by cree. My question is: Do I need to insert heat sink under the substrate to avoid overheating and transistor damaging? thanks
Hello, I am designing circuit (using 0.18um). Usually, by biasing Vgs < Vthreshold of MOSFET, we can push MOS into sub-threshold region. My curious question is: How much value of Vgs is "good" as a "rule of thumb"? I have referenced to "Trade-offs and optimization in Analog CMOS design" book, and they supplied a good reference (please check t
157171 This is my PCB layout. And The IC was getting hot, from that, and while checking voltage across the multimeter it doesn't show any voltage and after removing the supply I found the 3.3V pin and ground is getting shorted which I have tested with a continuity test using a multimeter. I got to know that the ATA6561 IC wa
Hello, Im trying to set wave port which i brought from the CAD drawing, but keep failing to set it. the problem is since there is a gap between the 'object from the CAD drawing' and 'sheet for the wave port' I keep faced with error message all the time. the steps I've took so far is, ============================================= 1. draw the