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Hi All, I am using PIC18F46k80 in Hardware and for software MIKroc PRO and for programming using MikroC PRO library. My CAN initialize code is; Can_Send_Flags = _CAN_TX_PRIORITY_0 & _CAN_TX_XTD_FRAME & _CAN_TX_NO_RTR_FRAME; Can_Init_Flags = _CAN_CONFIG_SAMPLE_THRICE & // form value to be used
I'm trying to design a custom PCB for my ESP32 DevKitC project. Fortunately, schematics for the DevKitC are available for download here. There are just a few things I don't understand: Why are there so many capacitors bet
use of lockup latch is for resolve hold violation but doubt is that the when neg. edge flop followed by pose. edge flop both have different clock then lockup-latch is required or not ???
Hello, I'm fairly new in this Synopsys world. I had a chance to use DC and ICC a lot these days, and am trying to validate my design. Wrote in verilog, through DC, to ICC. So I have a question and had nowhere to ask other than this place here.. I know there's lot of requirements to be met in order to declare certain design to be 'valid' (
I am developing a test rig for my motor controller. Below is the image which shows a motor is connected back to back to act as a load with load resistor 156455 left side is the controller that will run the motor of 400W. Right side i am connecting another motor with a coupling in between and resistor R1, R2, R3 a
How can I device figure out if it's been connected to a standard USB 2.0 port that can deliver 500mA, or a proper USB charger that can deliver 1A or perhaps 2A?
There do not seem to be good probes on the market. I want to see a 5 MHz rectangular wave with 500 ps switching time. Is anyone aware of a solution of this problem?
Hi, I am designing a differential folded cascode with both P and N-mos input transistor stages due to my different input common modes. During my transient analysis while running across the corners i am getting some offset of 70mv at worst between the two outputs. How can i minimize this offset. note: I am giving a 0.3mV offset at the input an
I have been using ADP5070 DC-to-DC Switching Regulator with Independent Positive and Negative Outputs to convert +5v to +/-15V. Upon testing on the PCB, Desired Outputs are +15V and -15V on the independent boost and inverting outputs of the ADP5070 ic respectively. Outputs we are getting upon testing are +15V and +13.8V respectively. I have done
I have been using ADP5070 DC-to-DC Switching Regulator with Independent Positive and Negative Outputs to convert +5v to +/-15V. Upon testing on the PCB, Desired Outputs are +15V and -15V on the independent boost and inverting outputs of the ADP5070 ic respectively. Outputs we are getting upon testing are +15V and +13.8V respectively. I have don
doesn't Q2 Mosfet short the B2 battery to the ground? No. D5 permits current flow only downward (charging) through B2 (lower) battery, never upward (discharging). Refer BAT CHARGER.pdf and answer below question. Will the battery charge without shorting B2 now? Will the series battery voltage be +24V whil
But the process corner includes five types, FF,TT ,SS SF and FS Thanks
Hello, attached the picture of the fully differential closed loop feedback, which one of the configuration should be the standard one ? many authors refer to config 1 and mostly to config 2, while the first circuit provides inverting differerntial output to the input and the latter is non-inverting, 157117
i want to know the procedure for executing the cmos inverter using finfet in hspice? could you please send me the required library files
Hi Guys, I'm trying to design the op amp in the attached article. I'm using 100uA current source and I'm trying to make a bias circuit in order to make all transistors in saturation and I don't know how to make that. 157100 157101 157102 157103[/A
Aside from the CPU, the memories want different things. DRAM (optimized for cost) wants trench capacitors or at least capacitors optimized for areal density. Meanwhile "VNAND" (or any EE memory) wants an oxide / dielectric that well tolerates repeated current stress (which normal reliable FETs would prohibit) and high voltage programming f
Hello, I have a BIN file called "some_file.bin" I want to copy the contents of this file to another file named : "some_file_2.bin" However, while copying I want to skip every 4th byte. For example : Contents of "some_file.bin" : 0xA5 0x3 0x11 0x34 0x33 0x12 0x37 0xDE[/CO
A = b = .' size(A)=5x5 rank(A)=3 det(A)=0 So A*x = b does not have unique solution. Solution x is x = d + t1*c1 + t2*c2. Here d = .' c1 = .' c2 = [
Hello, I have designed a custom development board for DSP controller. The power circuit (delivering 3.3V to the board) I have used is not working. I am sharing the power supply circuit schematics. 157108 Till now I am thinking that while soldering, the IC get destroyed due to which it is not working, but I am not sure. Pl
hi i saw in a file( i did not find the file again) that for layout of nmos transistor , two polysilicon layers was used for connection of gate to other segments. why two or more polysilicon is used for gate in cmos transistor layout?also why multi layers of metal is used for connection source or drain to other segment? excuse me if this questio