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Hi, I am using the following code, but intterupts do not launch once the RB0 goes high. Hi darktangent; I don't know this proc nor this compiler exactly but ... try out this (look at the red lines): #include #include #pragma config WDT = OFF void chk_isr(v
the resistors (and the capacitors of course) will not alter the DC response as long as the p mirrors are nor squeezed out of saturation. The resistors could help with current matching if Vref is larger than the opamp input OP. This bandgap needs a startup circuit no matter your changes. The capacitors in this configuration might hinder stability at
Since you didn't provide RTOS name nor names of O/S function calls, this is like saying my car is broke so what is wrong with it (and not specifying the make or model or much more about the car). Just guessing that you should change priorities of tasks, and ensure all calls from interrupts are safe and can be called within an interrupt. I could
EPROM at least 256 MBit, Flash 2 GBit for nor flash, that is suitable as program storage without error correction the 23L25611-10 I found after search is not UV erasable. Is there any such big eprom uv erasable? Sorry for the silly question..
HI Deepon I do not know Spectre that well, still I can tell you that the netlist is messed up. The netlister did not add the correct model type, nor its w and l (assuming these properties are common to my RNPPO in UMC18 CIS PDK) So you have a netlister problem which can come from a missing techfile: did you attach the techlibrary to your (...)
Hi: Anyone can Help me that in design compiler, how to transfer verilog file my.v into schematic view with technology myself,e.g.,tsmc,but not synopsis provide? I add target library and link library with tsmc in design analyzer, but after elaborating, my.v is composed by some module "GTECH nor......",which is not identified by myself (...)
Hmm... I'm not sure I follow you, nor understand your dilemma... In your code A is a function taking a float (parameter B) and returning a float (0.0). I see no other way of interpreting this? If you call A somewhere, like this: float f = A(3.74);[/
Hello, I have a question that might be unclear as I am not well informed nor at ease with the whole IBIS/Models/SPICE subject. I would like to know it is possible to use IBIS models (of electronic boards) to make some kind of a functionnal simulation, using CADENCE software, or do I have to somehow convert it into SPICE model => in that case,
I guess from your H-type gate structure no reasonable W & L values can be extracted (check your layout netlist!). I suppose this is a relict from a nor gate, where the 2 pmos input gates have been connected by a perpendicular poly connection. Such a structure will create weired or undefined W & L layout values. Remove this connection
Where are you getting your start and stop pulses from? Are the the correct logic levels and the correct timing? One problem with your circuit is you are toggling both flip-flops but you have no means to reset the state. I would use one flip flip & use the start pulse to clock the flip flop and the stop pulse to reset it. I am not sure the LM334
Hi Jackg, It is not related with bandwidth nor with averaging. The relation gain=output/input is to be thaught when the output reaches steady state. Maybe you are confused by the fact that an ideal integrator never reaches steady state (otherwise stated, it takes an infinite time). But in the limit (when t->infinity) the ouput goes to infinity
Maybe nikhilele is not aware of your capabaility, nor i am. so before asking help, make sure that your request is understood by others properly. and dont be rude when you are asking for help. nikhilele or nobody is nobody's servant here ---------- Post added at 21:28 ---------- Previous post was at 21:26 ----------[/S
A supply voltage of only +5V may be not enough power Neither TLE2027 nor OP07 are specified to work from a 5V supply. OP177 is, but the common range may be unsuitable though. I'm reading their datasheets now, but they are not helpful. In other words, you don't know what they are talking about? You should try to iden
I am designing a simple two input nor gate. But I get an LVS seems that the nmos which are parallel are not merging. In the LVS error report I get: ================================================= =========Matched Instances with Bad Net Connections====== ================================================= Schematic Instance: M
You can synthesize your RTL, make formal verification and static analysis without any simulation. But I'm not sure about input file format for Formality (if it's not verilog nor VHDL you can use this flow). But if you are going to make any simulation you need to ask your library vendor about any rtl (verilog or vhdl) files.
Hi, actually you dont need to modify you lib, even if I can figure out why you want to do so. You can simply use the “set_dont_use” cmd and cell footprint to tell DC to use nand or nor CELLs in mapping phase.
May be for you a nor monostable made with 1/2 CD4001 is enough.
Neither the maximum nor the minimum frequency is limited by the table length. You're not required to use a fixed number of samples for a sine cycle. At higher frequencies only some of the table values are used, at lower frequencies, samples are repeated. Phase respectively amplitude noise is introduced by the limited table resolution. For a method
You can't afford to ask me to learn something from you ;) you are right about that one: I have no time nor patience to spare on you.
"Once you have configured a timer in mode 2 you do not have to worry about checking to see if the timer has overflowed nor do you have to worry about resetting the value The microcontroller hardware will do it all for you."