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246 Threads found on edaboard.com: Nor Not
hi, i have purchased a car mp3 player with fm transmitter (china made). it works fine for some days. but now not working, neithor with PC (to add more songs) nor playing songs. only lcd back light is glowing. PC is not detecting it. I think its firmware is corrupted:cry: can any body help in this regard. for link to c it on net, go (...)
Youd didn't tell neither about used libraries nor which error you experienced. Assuming you're using ieee.numeric_std, it has no sra() function at all. Instead srl() respectively it's synonymous SHIFT_RIGHT() is determining the processing of sign bit from the data type. Use SIGNED type and you get signed behaviour.
Hi As I know VHDL can not model analog devive such as inductor and capacitor nor resistor and transistor. VHDL designed to model logic circuit and its signal delays.
When the opamp with feedback does not function as a stable amplifier - and when at the same time its output is neither at Vdd nor at Vcc (or ground in case of single supply) it probably will oscillate at a frequency fo. This frequency fo can be found in the BODE plot of the loop gain where the magnitude is 0 dB.
Depending on your requirements the matrices does not necessarily need to be square and of the same size. Missing data points (thus leading to matrices that are not square nor the same size) can be generated by means of interpolation. This scenario is common with measured data since equipment can sometimes fail and it would (...)
normally we used the combinational logic sitting between the 2 flops as combo logic..
Hello all, i would like to build a voltage follower. I found the scheme (see the attachment). Unfortunately, I am not able to get neither LM102 nor LM107. It seems they are obsolete. What other ICs shall I use. I need to track, as accurately as possible, 2 differential signals, 60kHz, +-100mV. Shall I employ bipolar of JFET operational amplifier
hii basha u missed nor gate
You should have posted in FPGA forum. Ok.this is a warning and not an error. this warning is saying that your sum_d_3_7 is neither initialized nor changes in your design. see if this signal is having drivers on it or not...
syrax, I know you are not an electronic engineer by profession, but you should try to draw a proper schematics. There are inexpensive to free programs for drawing schematics - you can for example try . The schematics as is now, does not show us the type nor polarity of the transistor, you even don't have a curren
A product Engineer has the responsibility of an IC once it is fabricated. The PE would not be involved with the design nor the Wafer Fabrication Process but is the interface between the manufacture of the IC and the final customer. The first responsibility is usually with the probing of the IC. The PE may be responsible for the Probe Test, the
I am writing a nor flash controller. I am not sure it meets the spec or not. Who can send me a nor flash model so that I can run some simulation to verify it?
hi all,i have little question of cst how can i polt the field of any antenna at any position(not near field nor far field) i make horn and put probe in my desired postion ,so how can i measure field I(i.e. how could i rotate the probe to measure the field pattern ) i wait so fastly ur reply
Many years ago, in 1960 - 1970 most popular was nor. Only DTL and RTL logic - in this technologic basis nor implementn more simple, then NAND. In multriemmiter TTL NAND most simple. This basis very popular in 1970-1980/ In CMOS not differerence, but tradition. Therefore - NAND ;)
80% is pushing it. If you want to reduce the density by 5%, then most likely it would require changes in design architecture. Neither synthesis nor floorplanning can reduce the density by that much, unless the implementation is drastically wrong.
Hi my frind There is no problem for 89s52 with lcd nither with port 0 ,nor with any port port1,2,3 I test all ports of AT89s52 with lcd with no problem port 0,may be not working with some lcd's if the lcd itself dose't have a pull up resistors ..... note that i said may be ... please upload your code and schematic to debuge and (...)
Just place C6 100nF (X2 type) before D1. Or add new one (better) Hi, I had a device that was failing with the conducted emissions test of the FCC part 15b. It was failing in the 800khz-1.2MHz range. I do not have a clock source of that frequency on my board, nor was I able to trace where it is coming from. My question is
Hi, The number of gate inputs to CMOS gates is usually limited to four for both sizing and delay factors. Lets look at the simplest nor gate (complementary logic) as an example. it is essentially 4 PMOS in series and 4 NMOS in parallel. Now, the more transistors you have, the more capacitance they introduce, and hence the longer delay. To
It isn't a good idea, nor is it a common practice to connect the output 0V terminal of a power supply to EARTH .. This would mean that the DC power supply is no longer earth free on the output .. In most cases this will not be a problem .. However, you have to be careful if the circuit to which you connect the power supply to has also some con
what about common mode noise / etc - as there is only a differential termination - there will be imo no real reflection damping for common-mode signals (neither at the receiver (diffpair-gates -> high impedance) nor at the transmitter (current source -> high impedance) - correct ? so what about elimination of common mode signals - not nice if r