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Let's say that I have a data. I want to use a parameter in RTL to provide the reset value for this data. parameter RESET_VALUE = 5; logic data; always_ff @(posedge clk) if (~reset) data <= WIDTH'd (RESET_VALUE); else .... How do I make this work syntax wise? Is it even possible? T
Hi, I have an android device and a PC. I am looking for a PC program to install in Windows 10 to implemnet the following feature. 1. Screen mirroring from android to PC: When the android device is connected to the PC (via a cable or wirelessly), I can open this Windows program and see a mirrored view (...)
Hi, As the title says, Im deciding on the power stage for a 5kW DC/DC application at 48Vin. Ive always heard that a H full bridge should be used for applications above 1kW, however the push pull has the advantage of using only 2 switching elements which could potentially reduce the overall conduction & switching losses. I know it has some draw
Hi I have built this in a single core 158580 It is from the page To build the primary I took a piece of 20cm wire, the
Hello, I need to parse the .out file format used to store the power calculated in the Time-Based Power Analysis by PTPX. The output is set by the command: set_power_analysis_option -waveform_format out Could anyone point me to some reference documentation describing the format? The file itself seems pretty straightforward but I need to be
by accident found that before checking the fp1,fp2 for coupling coefficient extraction you must set the port impedance to a value big enough for example 500 to 50000 no 50 ohm if this is 50 ohm there is no separation between the resonator frequency and see nothing like the figure below.158570
All Member, Please help me. I want to know what is to do compile this code, i do not know much this language/compiler they use, here are the code : #include // __CONFIG (INTIO & UNPROTECT & LVPDIS //What mean this // & BOREN & MCLRDIS & PWRTEN & WDTDIS); //What mean this __CONFIG (XT & WD
Hello, I am very new to formality and running a entire soc reference and its implementation for equivalence checking in formality tool. i am getting this report 20 Failing compare points (20 matched, 0 unmatched) 0 Aborted compare points 88545 Unverified compare points --------------------------------------------------------
Good day everyone! I just want to ask why the voltage at node N will decrease when Iref increases? Thank you! 158568
Hello everyone, I have been using eplan for a long time, but I have one problem that I cannot overcome. Attached is a photo, Not to put cross references on a terminal on the other side. If I do it according to the device, that's ok. But if I work towards the terminal, then it doesn't go through. Under number 2 I know what to do. and the probl
Hi, I wanted to know if there are any ways of generating a 10 sec digital pulse (0.1 Hz; 5 sec ON and 5 sec. OFF). I need it as an enable signal for a project I am making (the ckt. will be enabled for 5 secs. to sample the inputs and then disabled for 5 secs. during its processing). Similarly, how to generate a 1 sec. pulse (1 Hz; 0.5 sec. ON
Hi, really hope someone could help me. About the circuit" I am doing an in-memory calculation structure very similar to SRAM which has both write and read. The writing process writes data into the structure; the reading process needs some inputs and will do some performance with the stored data inside the structure then generates some outputs.
Hi All, I had a doubt in DFT 15000 testing. Let us consider this DFT 1500 is an IP and sits inside a module and this is the master module and it's controls the other module. Is there any integrated test for 1500 ip ( checking the scan connectivity for 1500 register) carried out. If so, can anyone explains generals procedure we should (...)
Hi, I am currently trying to implement the VHDL-2008 construct Generic Package. For this I have a generic type, which I want to initalize with a default record. Does anyone know if an if so how this is possible? I would like the colored part of the code to be similar even though it obviously does not work exactly like this. Code:
I pardon myself in advance for a partially philosophical question. Have me any device powered with 230V to 24DC and 5V DC , for standard home and office safety level, ground of device is connected to PE. In device is MCU and any digital input, we need to take them out of the device for general use, for example foot (...)
Hi A way of doing this Power supply spec??.. Vin = 1000v to 880v (source is 1000V but cable resistance between source and Power supply is 7.5 Ohms so actual vin drops with load) Vout = 48V Pout total = 12kW Efficiency 0.85 Pin total = 14100W Chosen Topology = In blocks of three Two Transistor forward converters with inputs stacked and
Hi All, Anyone has experience with this clause of the Def-Stan 59-411 part 3. We have tried to pass a couple of times. We have place a couple of MOV in the input stage and they don't dissipate the energy completely and there is always some damage. Is there any other method that we could applied? This is the close of the standard (...)
Hi, Can someone give me a simple example of this integrator formula, and confirm or correct what "s" is in this formula: Vout = - Vin (1/RCs) I understand that: s = jω ω = 2πf j = √-1 Is j = - 1? The formula is from Op Amps for Everyone, page 429, circuit named A-27, Inverting Integrator. 15
I have a pipe diameter(lets say 6 inch size). Water pressure flow rate 0 to 20 GPM. Pressure max. of 31 bar. Always there will be water available in the pipe. When there is flow of minimum 4 gpm, I want to get a signal that the flow is present. (signal could be relay actuating or any other form) I knew that there are commercially available pr
When an RTL circuit is synthesized for an ASIC technology, is to possible to trace back the original source code of the generate netlist gates? More specifically, I compiled an RTL IP using Design Compiler, and then I studied its power consumption in PrimeTime. But I saw that some modules are consuming strangely bigger than they should. However,