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# Offset Pipeline

21 Threads found on edaboard.com: Offset Pipeline

## Pipeline digital correction solve the offset of comparator, but not for other error

Hi, pipeline digital correction solves some offset of comparator, but it can't correct gain error, right? For example, for a 10 bit adc, the first stage is 1.5 bit stage, the idea gain of this stage should be 2, but the actual gain is 1.9. Even with the help of digital correction, it can not correct the gain error? right? How to understand

## Offset of dynamic comparators

Hello all; In pipeline ADCs where charge distribution dynamic comparators are used, the design of the different comparators is the same, they are only fed with different references to make them get exercised at different input voltage values.....When applying a ramp to the ADC each comparator exhibits a certain value of offset voltage (which is n

## Monte Carlo simulation of op amp with 90 dB gain

I have a 90 dB DC gain op amp I am using for a pipeline ADC. I am trying to characterize the 3 sigma offset with Monte Carlo simulation. The problem I am running into is that because the opamp has so much gain, any small offset induced by the Monte Carlo simulation causes the opamp to rail high and low. Does anybody know how to run a (...)

## Digital Error Correction in a 1.5 Bit Pipeline ADC

... how does it actually correct this offset? What is the exact mechanism that allows you to be able to tolerate a larger comparator offset just because you have digital correction. Find here a short overview on the RSD (Redundant Signed Digit) principle: 60106 A comprehensive description of t

## comparator in the 1st stage of a 14bit pipeline adc

our project is to design a 14bit 80M pipeline adc.The first stage is 4bit(1 bit redundancy) followed by 8 stages of 1.5bit/stage.the decision level of 1.5bit/stage is ?Vref/4,which can tolerated ?Vref/4(or ?Vref/2) offset.I dont know how people think up this method. and i dont know what are the first stage decision levels either. Could someone ex

## SFDR becomes worse with higher sampling frequency

I would imagine it relates to the settling time inside the pipeline(?) stages, finite time to get to sub-LSB error against a shortening period. Have you determined which element of the SFDR rollup is driving the degradation (noise vs offset vs gain error or whatever)? I am somewhat surprised at getting 60dB SFDR (1000:1) out of an 8-b

Hi, there, As is well known, the comparators in the sub-ADCs of a 1.5b/stage pipeline ADC can tolerate offset error as large as Vref/4, but why is it that ? can someone explain in more detail or post some links here, thanks! Added after 16 minutes: AND I also want to know which is the FIRST paper

## Question:Input Offset voltage of OPAMP of S/H of pipeline AD

Hi guys I have a question about the pipeline adc. In behaviour model of pipeline adc, every issue is ideal except the OPAMP offset voltage of OPAMP in SH. When i set the offset voltage of opamp in SH 2mV, the enob is about 8.8bit (9.9bit at all ideal issue). Here i am puzzled with this. Why is the influence of (...)

## Some doubts on pipeline adc

Hi guys, I have a question with regards to the parameters such as comparator offset, gain, capacitor mismatch etc.. in a given stage of pipeline adc. In general how much variation can you expect for the above paramters in terms of percentage with increase or decrease in temperature and ageing for 0.18um technology. Assume that the adc is working

## How to make each stage of pipeline ADC behave similarly?

Hi guys, I would like to know how to make each stage of pipeline behave similarily as close to each other as possible. I mean the multiplication factor of residue in each stage should be nearly same among all stage of pipeline. Its doesnt matter if there are large errors in each stage but the error factors like the comparator offset (...)

## How large is the typical DC offset voltage of a pipeline ADC?

One question, How large is the typical dc offset voltage of a pipeline ADC? How it degrade the ENOB? Could we say if the dc offset is larger than 2LSB, the resolution is degraded by 2? Thanks,

One question, How large is the typical dc offset voltage of a pipeline ADC? How it degrade the ENOB? Could we say if the dc offset is larger than 2LSB, the resolution is degraded by 2? Thanks,

Can to reduce offset in input terminal ?

## How to avoid unwanted comparator switching of flash ADC comparator?

high speed ADC 1. pipeline 2. fold 3. flash 300MHz flash A/D can use "switch comparator" use switch Cap .. and clock will do auto zero (cancel offset ...) comparator use "preamp + latch " for high speed signal you cn find many paper talk about this A/D

## Help me solve an offset error in pipeline ADC

Hi, This is regarding the offset error of a pipeline ADC (9 bits) with sign bit. Generally offset shifts the entire output transfer curve, hence doesn't change the shape of it and also the code width. I have few questions: 1). Is there any upper limit for the offset value? If yes, then does it depend on the speed (...)

hi,guys I am confused that why makes addtion of alll stages' digital output can correct the error such as comparator's offset introduced. Expecting your comments, thank you very much. san

## What's the maximum tolerable offset, without digital error correction, in comparator?

Dear Suhas, I think that it depends on the number of bits you resolve in each stage of the pipeline. Vref/4 would apply to about 2 bits per stage, if I am not wrong. Also, the residue gain is also critical in defining the required offset.

## How to simulate the offset of a switch-capacitor comparator?

Just intentionally add idea voltage source with finite dc voltage on one of your comparator to simulate the offset of the comparator.

## testbed setup for INL,DNL,SNDR,FFT...

But there are all ideal componet, such no offset of opamp and comparator, resistor mismatch, is this method simulation results can meet the real performance reqirements?

## Error in the ADC causing Vin-Vout characteristic to shift

Hi all In the sample and hold stage of a 1.5 bit pipeline ADC converter, when i get the Vin-Vout characteristic of the stage (the one with the triangles), i have noticed that the whole characteristic is shifted up by 60mV. I suppose that this is the systematic offset error which is not so critical (according to some books ). Am i wright? What

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