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38 Threads found on edaboard.com: One Bit Ram
Here is a picture of the Dual Clock FIFO used to "transmit multi-bit signals from one clock domain to another" and it is "usually implemented as a wrapper around a dual port ram". It is from a book. 131786 It is not clear to me when exactly are the signals full and empty asserted. Why does signal full only goto the "wr
I want to make one single board 8 bit based computer for academic use to replace my old 8085 and 68 series from Motorola which I earlier made About only 12 years ago, when it were already quite available cores with 16 bits, I worked in a company whose flagship products were based in another 8-bit variant of the Z
If you answer the question from the ram chip perspective, there will be e.g. 4 byte-wide ram chips that hold the 32 bit data and get the same row and column address. In so far the data is stored in one address. But the cpu data model usually represents the data as four bytes with consecutive addresses. Consider that (...)
Which one? ROM, ram, Sram, Dram, Fram, Mram, FUSE cells?
Hi Everyone, I wanna describe a ram and ROM in VHDL and am not really getting what to do, so I will really appreciate if someone can help me. Memory 8-bit Addressable Memory, i.e. 8-bit wide Address Bus; 4-bit Data-In-Bus; 4-bit Data-Out-Bus; one (...)
Hello everbody, I am in a very big project with an ALTERA FGPA Cyclone IV. This FPGA is going to control several systems and every system has its own configuration file sent by SPI protocol which it is already implemented like a VHDL module in the FPGA. In the start up of the system, the FPGA is sending the intial configuration file for a defa
That's an old one! I haven't used on of those in maybe 20 years. You can read it just like a static ram, make the CE pin low and put the address on the input pins, the outputs will show the 4-bit data. It is fully static so you don't have to worry about timing or clock signals. Brian. Ok, so I will be probaly be a
I recently posted in the MCU section about some projects with microcontrollers and FPGAs that I am planning to do, in order to learn. I have had experience with Verilog simulations and coding on Xilinx and Modelsim. I wanted to learn to actually program a FPGA using a Development board. I was comparing between, BeMicro SDK, the DE0 Nano, the
Hi, I have a doubt regarding the ddr 2 meomroy. I have processor to DDR2 interfaces where I am interfacing 2 nos of 1Gibt DDR 2 rams. Each ram is 16 bit data wide. I am using 32 bit data from processor to two ddr 2 rams. Instead I can use a Single 2 Gbit DDR2 ram which (...)
It sounds like you only need ram not EEPROM for your data storage so simply look at the web sites of microcontroller manufacturers for a suitable one. They are likely to be 32 bit or possibly 16 bit if they have that much memory. Also, consider whether you really need to save all the values. Minimum and maximum values and (...)
A type definition isn't a statement, by the way. A parameterizable component that expects port signals of the std_logic_vector type must be connected to signals of the second kind, if you want them one bit wide, e.g. a ram with 1 bit data width. You can't use std_logic in this case, but (...)
I have a FIFO of width 8 bit. I want to read 16 bit in one read cycle from that FIFO in every read cycle. How can I do that?
Hello everyone, I'm trying to implement a simple ram (for the SP601 evaluation kit) that will store a 12-bit data. I've seen many sample codes from XST user guide such as this one library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using (...)
Hello Friends: i'm trying to do one bit simple calc(using 8051 MCU) , which can take two numbers and operator from the Keyboard (save the numbers in ram) then do the math the problem i'm facing , i end up having wrong numbers when reading from ram . here's my asm code: ORG 000H JMP MAIN ORG 003H JMP INT0 (...)
Brams are not one big solid memory, but lots and lots of small ones (IIRC, they are 9K bits per ram). They can be configered to any combination of data and address, eg. 8k x 1bit up to 256x32 bit. You can infer Brams from VHDL, and the synthesisor will place (...)
Welcome to edaboard. :-) 2) What does a USB transmission consist of? Is it like a RS232 one? (start bit followed by data followed by parity bit followed by stop bit). From the microcontroller side it is exactly the same. For both USB and RS232, serial communication via UART needs to be implemented. You will need a USB to U
Hi, Thanks for your apply I don't want to use coregen. I want to code dual port ram with one port as 8 bit read/write and other port with 4 bit read/write. is it possible in xilinx or not?(I mean with vhdl code not with coegen)
hitech, You could take the bit stream, convert it to words, 8-32 bits. You can then store those in a FIFO and take them out on the output side of the FIFO as needed. A FIFO can be implemented in a duel port block ram. one side is writing the bits, converted to words, and the other side is reading them (...)
About process i heard probably from someone at my university. It is really good to read that its diffrent. So what is the most important in RTL? And what about compare two vectors? Should i search other way? I need to use that with counter, out signal is '1' when counter is above chosen value.
i would like to say AT89S52 cheap and best, easy to program,, part of college curiculum almost every one knows about it.. AT89S52 its 8 bit controller with 8K program memory 256 byte ram 32 io pins, UART, interrupts, timers In system programble