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Open Drain Cmos

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12 Threads found on edaboard.com: Open Drain Cmos
This is not open drain per se, the 50 ohms looks to be on-chip. I've seen / done a few open drain TX ICs but this has not been the norm since the '80s. open drain has its uses still, but standards is where it's at and your customer will tell you what they prefer (or, as a merchant (...)
On the transistor level, it's an inverter followed by a open drain PMOS transistor switching to Vdd. On the gate level, use a tristate driver with high active enable.
Suppose if i take an npn transistor and apply some voltage at the base the transistor will be ON and the emitter is grounded and the output at the collector is 0V. Similarly if i make the base cutoff the emitter is open circuited and the current is 0, the collector output is supply voltage. Now my doubt is when you say open circuited does not mean
It depends on source and drain voltages. Anyway if drain and source and gate were open, the output voltage would be float (High zero or High Impedance).
Look out for: 1. Power, Output or Input (can be latched or passive), Bi-direction In & Out (usually for data bus to Read & Write) 2. 3.3V (maybe 2.5V and 1.8V, if available in CPLD. FPGA usually has). 3. I know some CPLDs give you the option to use Tri-State, open-drain and even Schmitt-Trigger. Default is cmos drive. Depending brand (...)
I think the problems are quiescent current and SNR. Lets take your OR gate as an example. If one input is tied high, the other could either be high or low or anywhere in between. Lets say that a PMOS is open and charges the output to high. If the NMOS of the floating input opens wide enough to build up a drain current, it might discharge (...)
Ope drain or open collector are nromally active low types of output.
The amplifier has to be in linear region for starting oscillation. Probably you are using an inverter gate. In that case, a resistor between X1 and X2 is needed (10K to 1Mohm if it is a cmos). When you open the drain, the buffer sees a different load, and the amplifier as well. Probably this perturbation is responsible of start up. (...)
What does the cmos characteristicks say? Does it open with 2.6V? is the channel marginary? You have to consider also the application ( if I am not mistaken). What will be the voltage accross drain and Source in your circuit i.e. for a transmission gate with 2.5V on each side, a 2.5 V GD voltage or GS voltage simply don't do the job. Check (...)
Similar to what the others have mentioned, open collector (or open-drain outputs for cmos) are used for level-conversion and/or wired-AND. An example of the first feature is when you want to interface 5V to 3.3V circuits, or if you want to drive circuits with a high Vcc. The second application is used in shared buses, where (...)
Pushpull may be wrong term at the microcontroller. Sink/source capability and pushpull are different models. But complementery two open drain or collector output known pushpull. Most comman output types are totem pole, open collektor and active pullup type outputs. (cmos and open (...)
Hi, is propagation delay of interest?? (building a circuit with multiple voltage shifters) ... or simply build an open-drain styled outputstage using e. g. FETs that is driven by your Spartan II) Can you give us more information about your application?? regards, Maddin