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51 Threads found on edaboard.com: Ota Cadence
Hello Can any one help me in calculating THD, HD2 and HD3 in cadence. I am designing an ota. I dont know what sampling frequency to use? In some forum I have read I have to calculate DFT aswell for THD can any one help? Thanx
Please can anyone one help me in calculating the noise in VRMS. I have got the noise in cadence in uV/sqrtHz now I want to convert the uV/sqrtHz in Vrms. I have the noise result attached. Do I have to use calculator if yes the how? I want to calculate PSRR in cadence of an ota. Can any one help me step by step procedure to calculate PSRR (...)
Vdc=0 would be suitable for an ota with bipolar power supply. Nothing has be said yet about the test setup details. Technically, gm versus vid can be measured either in AC analysis with parametric vid sweep or by differentiating Iout = f(vid) obtained in a DC sweep. Considering existing tool features, the latter is probably easier to achieve.
Hi there, I'm making an ota layout in cadence, ams 0.18um (cmhv7sf). The only DRC error I have is about I/O wirebond - it says that some transistors don't have body contact while there are n-well contacts. When there where contacts on the left and right side errors where the same. 133931133932
you can simulate DC simulation after that you go to results --> Annotate DC solution . the DC current is noted in the schematic and you multiply by Vdd to obtain Power Consumption
Hi I am designing a two stage ota using cadence . Need to run monte carlo simulation for offset voltage. can somebody give me any user guide. Thanks.
Hello guys, I'm new on cadence and I'm designing the layout of an ota and on the LVS I have encountered the following message: "Unmatched Internal Nets" I think regarding the connection between: ->The bulk and the vdd! of the transistors (WHITE on the image) ->The connection between the bulk and the com_diff net (BLUE on the image) The imag
i wanna design and simulate bulk driven ota Which type of transistors should I choose (for bulk driven mosfets) ? ( pmos2v , pmos2vdsw , ...) cadence ic TSMC 180nm pdk
Please be clearer. I am not sure what do you want to do. If you want to create your own ota based on your design, just draw the schematic.
Hello All, Question is really in the title. I have a folded cascode single stage ota. As there are cascodes on the output drivers I am concerned as to what the Rout of the ota actually is. Does anyone have any suggestions as to the correct procedure to measure the output impedance of an ota? As a suggestion, should I place a (...)
Hi, Could anyone help me out to plot the linear range of a single ended ota, I mean the test bench to plot the input differential voltage V/s the output current. I am trying to plot the curves but I guess my test-bench is wrong. Pls help me out
Hi all, I'm designing an ota in weak inversion using cadence. I found the threshold voltage of each transistors working in weak inversion are different and they are also changing with applied gate-source voltages. Does anyone know how it happens? Thanks in advance!
Hello, I'm drawing a 2 stage fully differential miller ota with 2 CMFB networks. These CMFB networks are ideal and contain a vcvs with a gain "Acm". However, when I put 2 instances on my schematic and use the ADE (Analog Design Environment) to retrieve the variables I only get 1 variable Acm for the 2 blocks. I wish to control them independently
Hi, I am trying to plot gm/id vs (id/(w/l)) curve of a transistor for design of ota, i referenced many suggestions in the community but none of them is giving a clear idea about how to plot the above mentioned curve. I am able to get the plots for gm/id vs id , but when i am trying to do the parameter sweep w/l and ch
hello,i have using cadence to design the basic ota but i cnt get the correct ac response... How to determine the value for Vin+,Vin- and Vbias? 87232 87233
hello, Can someone help and guide me to design third-order ota-C type filter using cadence? the below attachment is i found from somewhere abt gm-C filter but i dont know the ota in transistor-level simulation model... hope anyone who have experience to design it to help me..(urgent!!!) thanks a lot.... 87148
I am a beginner in cadence,I am designing a two stage ota. My design has folded cascoded configuration in the first stage with class AB along with current mirrors in the 2nd stage.I have attained saturation for all transistors except for one,which is now operating in linear region. My output shows amplification,but i get a triangle wave with ac ga
FATAL : "Attempting to write a file that is not open. Open a file first then you can write to it. May be simply your path/fileName isn't correct?
yes, add input signal to design in testbench view as Vcm and diff signal on top of it, ( simply connect vdiff to pos input of ota with mag of 1, and vcvs with gain of -1 to neg input,) and then run your ac simulation. Ofcourse instead of selecting Vout as in amp u should select Iout . from the resulting plots (ac simulation result ) u get what u n
Hello every one, I have attached design of programmable ota. but i dont know how to measure parameters like gain, phase, CMRR, PSRR, slew rate etc. To measure all this parameters i have used one test bench which is also attached here. But problem is that i have measured gain in db, which is negative and phase is also negative. In test bench th