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205 Threads found on edaboard.com: Ota Gain
HI I have designed a capacitive feedback ota ( ota is folded cascode single stage ota with ideal CMFB). When I simulate the loop gain of ota (using iprobe and stb analysis in cadence) I get a 'High Pass' response at low frequencies. I am not sure why this is happening. Please help to solve this issue. (...)
Hi I have designed capacitive feedback fully differentail ota. I am trying to simulate loop gain and step response of ota. Fig1 shows the test bench used Fig2 shows the loop gain and fig3 shows the step response. I have following questions 1. Why loop gain curve is not flat at the beginning? Theory (...)
Your amplifier is not a 2 stage one strictly speaking. It has only one high-impedance node (the output) and the diff-pair itself does not provide a lot of gain since it is loaded by diode connected transistors. Compensation is also done differently compared to the two-stage Miller compensated otas. Here you compensate with the load capacitor. This
I have to design a 12bit , 100MS/s pipeline ADC. First I have started the design of the ota for the front end S/H. I have derived the required DC gain and UGB required for the ota. Now how to fix the load capacitor size for the ota.When we use this ota in the S/H , what should be the size of the sampling (...)
ota's are designed to be the gain stages of an opamp. the result is a high output impedance. This can sometimes be overcome by the very high gain. An opamp provides an ota with a current gain stage to act as a buffer. In some cases the buffer is too expensive or undesirable, making the simple (...)
My gain is an expression for a four stage ota gain, which i want to sweep with my input Common mode level. I guess there is little clue to what-to-do in your reply !
I am designing an ota for my GmC filter, and I have question regarding the THD simulation. In, papers, I find THD results for the ota while sweeping input signal amplitude. However, I am not sure if the output is left open for this simulation. for example, if the ota gain is 40dB, then for a 100mVpp input which very often (...)
I am trying to design an ota in 0.18 ?m CMOS technology. My targets are: Av>60 db ω (unity gain)>1.2GHz Slew rate>200v/?s I want to know: is it possible to design a telescopic ota WITHOUT gain boosting scheme to reach the above metnioned characteristics? I like to design a very simple traditional telescopic (...)
Hi all the attached is a booster amp used a gain boosted ota, from one berkeley student's project report. I don't understand why he used cascoded tail current source with one transistor controlled by biasing network and another by cmfb. Any particular advantage of this topology compared to normal cmfb tail current source (two parallel transi
Hi BillQ, at first, I don't think that common mode effects are responsible for your observation. The main point is, that in both cases (loop open/closed) the amplifier should have the same bias conditions. Secondly, it would be very helpful if you could tell us something about the type of your "amplifier" (opamp, ota, BJT, FET,...?) and the su
Hello all, For the choise of the unity gain frequency of the gain boosting amplifiers we have the basic equation : β*funity,open loop,otagain boosterota Sorry, but I don't see any "equation".
I know this has been asked a million time and I have read them all and have followed some of your suggestions, but still get unreasonable measurments. I want to measure CMRR and PSRR. I did a monte carlo simulation as suggested and added up to 10% missmatch in the input devices and measured the output gain through a VCVS where both outputs are t
Hi, I have to design a Folded cascode ota with gain>50 dB, Unity gain frequency 25MHz, Phase Margin of 60 degrees , PSRR>55dB and CMRR> 55dB for a 5 pF capacitive load. I am able to satisfy all the conditions except the Phase Margin of 60 degrees. I am getting a phase margin of 70. How can I bring it down to 60 without affecting my (...)
Hi, I want to simulate with Hspice, the fully differential ota such as, AC gain and phase margin. Generall speaking, fully differential amplifier has two input vin+/vin-, two outputs vout+/vout- . I know the differential mode gain is Av=(vout+ - vout-)/(vin+ - vin-). But How I do this in the Hspice. The circuit that i simulate (...)
Hi guys, I want to test (not simulation) an ota as is shown in the figure. This test method comes from one IEEE paper, but I have one big problem with this testing method, which is the offset of this ota. The ota is a folded-cascode amplifier with gain-boosting which is to be used in the sample hold amplifier in ADCs. I (...)
I want to design an ota for SH circuit in Pipelined ADC and some of the important specicications are, Vdd=1.2V VCMI=VCMO=0.5V Adc>96dB GBW>400MHz SR>300V/us CL=Cc=5pF(for low-noise) The two stage folded-cascode gain-boosting ota with hybrid cascode compensation is chosen to meet the spec(the circuit woul be given in Fig6). The AC (...)
Hi all, I am designing a folded cascode ota with gain boosting. I am trying to figure out the right topology for gain bost aplifier. I came across the paper from Bult 91 where he mention that it is necessary to have a additional stage with "input common mode range close to the supply voltage". Then he goes on to suggest using folded (...)
Hi All i am designing a telescopic ota with gain of 50 db and UGBW of 50 MHz. i am able to achive 50db but my UGBW is stuck at 11 Mhz , i want to increase this but it seems i cant change it i am using a telescopic Cascoded ota
I uploaded af paper about Miller ota based Gm/IDS Methdology!It's short and simple. I understood everything except the concept of finding the Early Voltage VA3,VA4 through equation 1! From design specifications we know the overall gain Av(dB)> 80, not Av1. How do we know and calculate Av1 dc gain? I would appreciate if someone (...)
This is result from a ota simulation. The ota is a basic folded cascod ota with differential PMOS input stage,connecting a folded cascode output stage. The x is Vod( differetial output voltage), the y is Rout. Any one can tell me how to get this result, How to set up the simulation.