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19 Threads found on edaboard.com: Overdrive Comparator
That's a lousy test method for such a detailed question. You embed time-domain low-overdrive errors relative to a DC Vio spec / interest. Testing of real comparators tends to put them in an integrator / divider loop which gives you a high gain measurement point and gives the comparator a quiet low impedance drive at the inputs.
I presume your hysteresis plot is recorded as static transfer characteristic. The transient test signals may be simply too short to trigger. The comparator behavior can be characterized by a response time versus overdrive curve. Fast response needs some overdrive beyond the 790 mV point.
This probably involves the underdrive/overdrive of the inputs. Inspect the common mode, pre- and post-transition difference voltages. comparator transient performance specs are often quite specific about how "wound up" the front end is initially and how much past null the input transition goes, which affects the degree to which the front end is st
hi guys, i designed a comparator and would like to test it for features like : aol,gain,overdrive,offset,slew rate and more my question is are the test benches for amplifiers is good for comparators? and if so , why ?? tnx
I very much doubt a practical continuous-time CMOS comparator operated at such low power will come anywhere close to a 5mV Vio, let alone enough less that you consistently get usable overdrive from a 5mV over-step. Mismatch gets worse as you starve current. Clocked designs can at least give you an autozero to make the most of the (...)
At ATE test, I expect we would ramp (step) the input difference upward, record first "1" and then from a positive overdrive, ramp down and record first "0". Then it's arithmetic. However this is liable to be statistical / noisy numerically and has never, once, been a clean test development or a totally clean production test solution as far as my r
If by "operate" you mean full rail-rail swing and 500MHz toggle rate with a usefully small input overdrive, that's going to want some exotic technology. Says to me that your GBW product ought to be about 50GHz (figuring you'd like less than 1% input gain error so A=100 at speed). Now the more input error you can tolerate, the lower the GBW can
First, you need a comparator with a low-overdrive prop delay of maybe 1nS - if you want to allocate 1nS to input settling time including kickback noise, and 0.5nS to the encode logic. If you want single cycle latency which is the whole idea of a flash. "Low overdrive" means VIN/2^(N+1) roughly - give it half of the "bin" voltage for (...)
Hello MCP65 comparator DATASHEET ...the foruth line down from the top talks about "overdrive".....may you inform what this is?
How to characterize the performance of a "Track and Latch comparator"....? As with any other comparator: sensitivity depending on comparison level and overdrive hysteresis depending on comparison level and overdrive switching times depending on comparison level and overdrive propa
The risetime is what will respond to loading changes, and depending on how you define "delay" you could see up to 50% of that risetime (falltime) as a variable delay adder (if your definition is based on the output 50% voltage swing point). comparators also have an input overdrive sensitivity which for slow-moving signals can really push out delay
Hi all, perhaps a stupid question, but in a certain CMOS process what is meant with underdrive/overdrive options?
You probably have some elements of delay which respond well to increasing bias current (back end delays) but the front end gain is key to low overdrive comparator delay, and this can be kicked around a lot by temperature, yet not respond much to bias current. It might be that you need to compensate this differently than the back end delays, to make
The lower your edge rate, the greater the multiplication of voltage-domain noise to time-domain noise. The comparator itself wants to be fast and have a very narrow linear input window (i.e. fast at low overdrive). But nonetheless, look at what P-P noise amplitude you can get on the timing ramp and how long the ramp dV/dt takes to pull thro
Hi, How to decrease the delay time of this high speed comparator, please? In my design, the delay time from input to output is 11ns when the load is 5pf and overdrive voltage is 10mv, I want to decrease it below 10ns. In my design, the delay time from input to latch output is 5.8ns, how to decrease it, and the delay time from latch output to out
There are many ways of doing this. One way is to monitor the prop delay at different common mode input levels with different ~100 mV (or any) overdrive at the inputs and make sure it doesnt degrade. The other is the monitor the threshold (and thus offset at the transition point) of switching voltage produced at different common mode input levels.
Usually it is 100mV step with 5-20mV overdrive .. Step represents the voltage change necessary to switch the input differential stage fully from one state to the other .. To understand what an overdrive is read the following quotation: If the input voltage to a comparator is more positive than the reference voltage plus the offset?VOS
that's digital though.. analog test does not use boundary scan, etc - you would sweep though the threshold of every comparator and watch it trip. Now extract offset, overdrive, etc. Analog test is actually a big field, but a few quick rules of thumb are: 1) Add test mode to allow testing of single blocks, or other options such as turn off oscil
How comparator input overdrive and propagation delay is related ?? Hi all, are you considering an op-amp with internal compensation? if the op-amp input stage is saturated, there is no more dependance on the input signal amplitude due to slew rate limitation and compensation capacitance. If you consider an open loop or hyster