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12 Threads found on edaboard.com: Parameter Veriloga
// veriloga for ELC612, Analog_Timer, veriloga `include "constants.vams" `include "disciplines.vams" module Analog_Timer(start,Vout); input start; output Vout; electrical start, Vout; parameter real ton=10u; parameter real Vmax=1.5; parameter real vtrans_clk=1.65; parameter (...)
Hi all, I'm trying to simulate a current-controlled current source written in veriloga. Here is the code: // current-controlled current source // current-controlled current source module cccs(p,n,pc,nc); inout p,n; input pc,nc; electrical p,n,pc,nc; parameter real gain=0; analog I(p,n) <+ gain*I(pc,nc); end
Hi all, I design 3bit idea DAC using veriloga to decode the signed binary to decimal. My purpose is change: 100 -> 4 011 -> 3 010 -> 2 001 -> 1 000 -> 0 111 -> -1 110 -> -2 101 -> -1 I used modelwriter tools in Cadence Spectre to design DAC with parameter (max voltage = 4; min voltage = -3, threshold = 1). However, its result is wro
I am trying to build the model of a current or voltage reference with a certain parameter that defines its spread with process. Anybody knows how to generate a gaussian distribution with veriloga during a DC Montecarlo analysis? I've tried with the $dist_normal, but didn't succeed. Thanks in advance, Sergio
You cannot assign a value to a parameter within the analog block. Try to define vd as a real only (not parameter real but just real).
Hello, I'm busy trying to find a easy way to vary parameters within my schematic during monte-carlo analysis by the use of veriloga-models. I tried to used the functions $random or $rdist_normal, but those seem not to vary throughout the different iterations, in a DC simulation I get a peak at a varying value but no standard deviation. I read
Hi, `include "disciplines.vams" module relay (p, n, ps, ns); parameter real thresh=0; // threshold (V) output p, n; input ps, ns; electrical p, n, ps, ns; analog begin @(cross( V(ps,ns) - thresh, 0 )) ; if (V(ps,ns) > thresh) V(p,n) <+ 0; else I(p,n) <+ 0; end endmodule Taken
1,there is an example of differential opamp wirtted in veriloga in the bmslib. You can add the parameter includes gain, gbw and slew rate. path:/edatools/cadence/ic5141/ic5141_200903/tools.sun4v/dfII/samples/artist/bmslib; 2,you can construct your differential opamp by model writer.
The random generator is a pseudorandom generator. Following excerpt is from the veriloga language manual. For each system function, the seed parameter is an in-out parameter; that is, a value is passed to the function and a different value is returned. The system functions will always return the same value given the same seed. This (...)
It seems possible. Try parameter. When you instantiate such a component, you can transfer info such as instance name to component internal using iPar (I am not sure. You need refer to the cdsdoc).
Hai everybody, My name is Raj, I am working on sigma-delta ADC. I am trying to simulate the 1st order sigma-delta ADC in cadence. In ahdlib there is a 1st order sigma-delta ADC, it is in veriloga code. can anybody help me regarding what values to be given to a parameter to get a output. And can anybody help me what the
You may use four terminal relay or a veriloga module: module switch(s, d, g); inout s, d; input g; electrical s, d, g; parameter threshold = 2.5; analog begin if( V(g) > threshold ) V(s, d) <+ 0.0; else I(s, d) <+ 0.0; end endmodule