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69 Threads found on edaboard.com: Phase Loops
0.39 Hz frequency difference means 2.8 degree phase error increase per sine period. You need a quite large coupling inductor to keep the error current within manageable limits. Or multiple frequency updates per period. The phase and voltage control loops have to be implemented in a microcontroller. Even it works, don't see the advantage (...)
Hi, I strongly recommend to use interrupt controlled regulation loop. This ensures a fixed timing. Fixed timing is essential for filters, PID control loops. Only with fixed timing you can calculate dead_time, delay time, phase angle .... Additionally you gain a lot of processing power for other tasks. Klaus
I have run into similar problems with stb, like it starts at a solution of no gain rather than peak gain. Never did get to understand why; expedience pushed me back to the old familiar AC method and calculator extraction of the gain & phase. It wasn't a consistent failure either, just enough of them in PA/MC loops to make the results look unreli
I doubt that the signal annotation in the diagram corresponds to a formally correct laplace domain representation. If you are interested to figure it out, I suggest to read chapter two of Roland E. Best, phase Locked loops.
Sir, i am trying to detect a three phases lines i.e which phase is available or not by using pic16f676 .(three phases like R, Y & B phases individually connected to pic16f676 micro controller pins RA0,RA1 & RA2 respectively) using series of 2.2M ohm 1/2 watt+5M ohm 1/4 watt to PIC pin RA0 and 10K ohm connected to ground & (...)
There will be 2 speed control loops and 2 field control loops with a reference voltage for each to match the outputs with no load. When combining 2 voltage sources with and without a load, there be stability problems to resolve with no load and mismatched source impedance ; winding , cable resistance and field regulation impedance. Current sensin
You should insert probe before inp input of opamp not at it output. Yes - thatīs correct. In case of two loops of equal "degree" you must open the positive feedback loop only. Otherwise you loose the dc operating point (stabilized by negative feedback). However, one can argue if this gives the "correct"
yes, but that has nothing to do with the problem here. Generate loops are unrolled in the elaboration and synthesis phase, and have nothing to do with the netlist. Hence this tetramax synthesisor is really bad. Xilinx, Altera, Synplify have not problems with generate loops, and havent done since Ive been writing VHDL.
Hi. Say I use command line to run simulation. For example in Hspice my input stimuli is like this: .op .options ingold=2 list node post .print ac vdb(6) dec 100 0.001 10g * net 6 = /out .MEAS AC gain MAX vdb(6) *gain .MEAS AC bandwidth WHEN vdb(6)=0 *Unity Gain Frequenc
Hello all, I'm preparing for my graduation project which is (a Verilog implementation of the all digital phase locked loop ) and asking if you can recommend me any good books or references about this topic, and any tutorials on how to make the chip layout on cadence and calibre . (i really don't have any experience on how to get the chip lay
hi dears i want to have some information about loran-c receiver. i want to know what are these terms? - what are phase tracking and phase-tracking loops in loran-c receiver?( -what is cycle selection(cycle identification) and cycle selection loops in loran-c receiver? -How can i track third zero-crossing in loran-c (...)
It's far from obvious that a ADPLL design uses a TDC, the basic ADPLL concept known from literature (e.g. Best phase-Locked loops) in fact doesn't. So to make your question understandable, you'll want to refer to the specific literature discussing TDC usage.
But when I generate Bode Plots for Closed Loop i see the Magnitude diagram starting from value of 0, and phase diagram starting from -180 Which gives me -180 phase margin. Hi mooma, you should know that the term "stability margin" applies to OPEN loops only. That means: When the BODE diagram of the open-loop transf
Hey everyone I've been scouring the internet looking for any information on frequency locked loops but it's been dismal at best. I'm not actually sure if a phased locked loop will do the same thing, but essentially I'm looking for something to automatically tune to a given frequency. Is there a real difference between FLLs and PLLs? If so, wh
In general, PLL's are 2nd order feedback loops. A zero is introduced so that at crossover, there is sufficient phase margin for stability. Above the loop bandwidth, it is desirable to introduce another pole for noise rejection (primarily, for rejecting the noise introduced by the charge pump, which operates at the clock rate). IMO, there is no pro
LTspice... I used it to simulate PLL too. Added: In real time and as Laplace blocks (function of theta, phase)
59590 Hi,i don't know how to make a simulation to test the phase margin for the circuit above, anyone who can help me?i have tried to break the point A and B to make the AC simulation,but the result is strange,I don't know the method i did is correct or not?Or is there any other method much better to measure the phase margi
I have designed two phase locked loops, one of which is covering from 1900M~3200MHz (VCO is from Z-comm,V600ME20) and the other is for a single frequency point for 1900MHz (VCO is from Z-comm too, V603ME) on the F4 PCB. The PLL synthesizers are both HMC700 chips. Now the pll can be locked successfully. However, when I shaked the shieding box in w
The classical PLL text book: phase Locked loops 6/e - Roland Best - McGraw-Hill Education See also previous discussions about PLL books at edaboard.
Hi, i need to design ADPLL in VHDL as PM demodulator. The best explained i found in Best, R. E. (2003), phase-locked loops: Design, Simulation and Applications, McGraw-Hill. It is something like 74HC297. Could you answer me these questions: 1. What kind of signal should be as an input if i receive almost sine wave from ADC, maybe between ADC a