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106 Threads found on Phase Margin Opamp
If number of LHP poles is higher than LHP zeros for only one, phase could never achieve -180 shift.
Hi everyone, I am simulating an opamp which has a fu in the kHz region. It happens that I am getting a very high gain margin (like >50dB @ 100MHz). Does anyone can tell me if this is good or bad?
The method doesn't differ for a folded cascode opamp. Suggest you search the G00GLE results for your question!
This indeed look a like stability issue for the opamp. With the probe in place, what is the phase margin and gain margin you obtain? Check with some initial condition on the capacitor, by inserting a voltage source in series with the capacitor.
The rated phase margin is ΦM=60 Degrees @ CL = 20 pF for 220pF the graph shows 40 deg PM YOu have RC 16k5 and 2.2uF which probably reduces the PM near 0. COnsider 1st opamp with non-inverting gain of ~4 and eliminate 2nd Op AMp to improve phase margin then reduce C8 and double R9 The reason is the (...)
Hi, I hope this is a sketch only. There are some issues. It looks like you connected the feedback path on the Gnd connection of the scope... The compensation of the feedback opamp is dubious, it seems to be made for low gain setting, but your opamp has no (local) feedback. Is it correct that the feedback opamp is inverting?
Hello again Iam sharing my results for my first OTA results the problem that phase diagram starts from +180 and I was thinking that phase should start from 0 degree - how can I fix that ? my 2nd question Is this opamp stable ? first two points for gain and phase and 2nd points for phase at zero gain (...)
Yes - such a gain peaking is caused by a phase margin which seems to be less than 60 deg (perhaps around 50 deg) - however, it is in no way "dangerous" (that means: not too small).
Hi all Im designing fully differntial folding cascode opamp and my opamp has: gain = 70dB, phase margin = 80. When I test for overshoot and setling time I see a 20mV overshot but the worse is taking long time to settle. Anyone can give a suggestion how to fix this.? Thanks a lot
Hi, what are poles and zeroes in a compensation network like Type-3 compensation for 2 stage cmfb amp. how we can boost phase margin without affecting Bandwidth. by using miller compensation cap, BW decreases. thanks Safiya
Hi, I have designed a folded cascode two stage opamp on 130nm process. The opamp works fine. Figure below shows the gain and phase response of opamp. It has 45 degree phase margin. Now the next step is to design circuit which generated the bias voltages for opamp. For (...)
Hi, I have designed a class AB opamp and then drawn its layout. After extraction I run post layout simulation but saw that phase margin was degraded to 40 degrees. I was wondering if there is anyway I can trim the circuit to improve the phase margin, so I don't have to redraw the whole layout, or I need (...)
Hi everyone, I'm trying to size the miller cap for a fully differential opamp. Without the miller cap, the phase is around -230 at 0dB (open loop, differential output). I guess, the opamp is not stable, but I try to run some simulations and I'm not able to see it oscillating! Anyway, I'm just wondering what should be the (...)
Hi, I'm trying to design an two staged Op amp for a sample and hold ciruit with 125v/us slewrate and GBW>50 mhz with 60 degrees phase margin. My main problem is that i can t fullfill both gbw and phase margin requirement. Am i doing something wrong or should i just use a different amplifier? I posted my test (...)
Hi everybody. I want to design a cyclic ADC and at this time I want to implement and design an opamp for this purpose. my ADC features are: Fs:20 MS/s Number of bit:12 could you tell me what the parameters are for opamp ? I design an opamp with these parameters but it doesn't work in my ADC. Gain=60 db phase (...)
Hi. I designed a folded cascade opamp with Hspice and I want to simulate it. I want to calculate dc open loop gain, Bandwidth, phase margin. How can I do that? please help me. regard. A.Jafari
Hi. I'm going to design a pipeline ADC and implement with real opamp. when I try to design opamp and implemented it in the ADC, my converter doesn't work. Does anybody can help me? pipeline features: Fs=120meg, Number of bits=12; opamp feature: fu=340M, dc gain=82db,I have enough slew rate phase (...)
If you know your noise requirement then you should be able to determine the bias current in the amplifier as the two are related (More current -> less noise). This also gives your transconductances gm1 in the first stage. Then depending on your requirement on the gain bandwidth and the phase margin you need, it is possible to determine the compensa
Hi. I designed a folded cascade opamp in the Hspice software and achieve these parameters: Gain= 87 db----phase margin=100',.... but I think that the amount of phase margin is not true so does anybody can help me? Does anybody have a circuit that shows me how folded cascade must get simulation in Hspice (...)
in usual opamp ac simulation, the phase margin(PM) starts from 180-degree or 0-degree, and PM=phase (when VDB(out)=0) or 180+phase (when VDB(out)=0); however, in bandgap core loop ac simulation (using two bjt to generate detaVBE, and using an opamp to force V+ = V-), the (...)