Search Engine www.edaboard.com

17 Threads found on edaboard.com: Physical Design Issues
Is this strictly a simulation or have you implemented your design in physical hardware? After only glancing at your code, two issues come to mind: 1. You got a code block define within main(), however there is no Superloop, i.e., while(1) associated with it. void main() { unsigned char msg = "Keyboard Test Program!\r\n"; unsigned ch
Hi I have started with cadence dtmf block pnr and following the lab .The problem is i am unable to address the issues .I need complete explanation what step to perform and what errors to fix at each stage ? the lab work is exclusively using gui its like fun play typing command and seeing the result.I need to address floorplanning,placement,cts,
Hi I have started with cadence dtmf block pnr and following the lab .The problem is i am unable to address the issues .I need complete explanation what step to perform and what errors to fix ?? how could i do that ?? the lab work is exclusively using gui its like fun play typing command and seeing the result.I need to address floorplanning issu
With respect to clock gate, what are various issues you faced at various stages in the physical design flow? plz anybody answe this question one more question for 2 year experience wat questions(topics) i can expect in interview apart from my project....
Simple, if you do not do physical design you will not have any chip in physical. Then no other domain will be there... Infact more PD engineers are required to solve the issues seen in 40nm and below.
Hi Friends, With a 5+ years of experience in the ASIC design, I have worked both in Frontend (SoC Integration, IP design, Verification) and Backend (memory compilers, Standard Cell Library design). Now I am thinking of starting own business in near future and wrt this i would like to hear from you guys following: 1> How do you see in (...)
What actually happens in power planning? What are the library files invilved in it? How to optimise it? How are power rings,straps,trunks are designed? Howvdd & vss lines are laid? What are the issues encountered while placing i/o pads?
Please do provide some solutions for these queries as i need to know the solutions Somebody correct me if I am wrong... 1. What kind of issues or a report does a Backend physical design guy give to the Synthesis guy ones he has received the netlist. And what checklist should be done by th PD guy before starting off the flow.
An engineer who prepares the physical drawing(MASK) of the transistors (circuits ) designed by the circuit designer. The Layout(drawing,MASK) that he prepares is sent for fabrication.
hello friends this is T. charan Teja from hyd .. ive comepleted B.tech in 2008 from Electronic background for my passion towards VLSI done diploma in Vlsi design (physical design) , but could not find a job posting in this domain. waiting hungrily for a job.. ive kept my resumes in monster, naukri, etc.. but could not get a single rep.. too (...)
Hi All, Can someone point to the kind of issues that the physical design team reports to the synthesis team, after the netlist is released to them for entire physical Flow. Thanks, Nik
See link
What kind of issues can be faced while physical design in each step particularly in Floorplanning Placement CTS Routing And ways to overcome them?Or can any 1 suggest some good book on PD which explains each step in complete detail
Hi friends, In the era of low power design, I hope power plan is vital. I am interested to know the recommendations for best power plan? Would u pl list the issues that are possible at power plan stage in physical design? Pl post the issue and describe how it was solved. issues related to straps trunks (...)
when technology changes design rules changes a lot. because design rule is to tkae care many physical phenomena .depending upon geometry migration it can be very small or it can be very large also . suppose u go from 0.8 um to 0.18 um technology the design rules which changes are manily like distance between two active (...)
Hi, Can any one discuss the various issues with deep submicron physical design and the ways to tackle them... Please reply
Hi, I'm encountering the following issues.. in my implementaion phase. Tool Used :: Montery (dolphin) Question :: How is the placement grid computation done in any physical design tool 'm also pasting in a part of the log report to give you guys a clear idea. Stage :: Global Placement " Info


Last searching phrases:

near far | nobody | mean well | forth | throughout | and nor | seven | and nor | seven | nevertheless