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48 Threads found on Physical Implementation
Structural verilog is (or can be) a dead match to the physical implementation (map to std cell library). It can be built from schematics easily / automatically, and vice versa. Seems like #3 is unnecessarily ornate with no benefit and likely longer execution time for simulations.
Hello, I'm designing a simple circuit using Multi Supply Voltage. I'm using synopsys Dc Compiler for synthesys, therefore I must use UPF. For the physical implementation I will use Cadence encounter which doesn't support UPF, but requires a CPF. Since my design is simple (I have only one power mode) the translation from UPF to CPF is sim
The enclosed gate layout (ELT)of a MOS transistor is a popular physical implementation in mitigating the effects of TID (ionising radiation) on normal device operation in Space/Cosmic environments. A couple of questions: 1/ I would appreciate knowing where I can find detailed classic information on the principle of the MOS enclosed gate la
Hello !! I have some std cells with the following pins : vdd, vnw, vss, vpw. FRAM views .lib Then, I have some other cells with the following pins : vdd, vdds, gnd, gnds. FRAM views and .lib I would like to make the synthesis and the P&R with ICC version : G-2012.06-SP4/bin/icc_shell Is it possible to use a mapping file ? or do I have to
Hi, I am new to physical IC design and I am working on CTS now. After CTS when I checked the clock transition time, it seems that rise transition time is different from fall transition time. Can anyone tell me why its different? Thanks!
in LTE physical layer implementation using matlab , the turbo decoder when operates only with AWGN it performance is ordinary but when i add the blocks of layer mapping and ofdm it has no effect on them that the BER is still equal BER without using turbo so i didn't know what is the problem !!! that performance with turbo should be better than with
Hi.. I am trying to imagine how a DC bus looks like physically. I have just seen DC bus as a "line"in diagrams. But in real life how does it look? Also, the voltage of a DC bus remains constant. How? Isnt it a waste of energy to have a constant supply to a DC Bus just to maintain the voltage? I am considering a PV system, a Wind turbine with rectif
Check below link:
Can you please explain it more clearly ? Cant understand net and wire difference ? Net is logical connection, which represents connections between two pins. Wire is the physical implementation of this connection using some metal layer.
please, i want to make my graduation project in lte by implementation physical layer in matlab .but i found this idea is repeated so if there any modification on this idea to make it much better.please suggest or any new idea but related to lte or generally wireless broadband but new idea and based on programming using matlab?
Hi , Can anybody explain me, will the instances may be flipped(side-wise) after placement legalization by the router (routing stage ) to reduce routing congestion?
I can't understand the stages of physical implementation (including syntheses, scan insertion, PnR, timing and physical sign off).
Ultrawideband (UWB) multiband OFDM physical layer with fixed-point transmitter/receiver modeling. Hope it answers your needs
Sunidrak, Gud to start with programming languages C,C++ and scripting languages perl,TCl and Cshell. Which will help you comfortable in the work environment. For verilog Hardware Description Language refer samir palnithkar. For backend implementation start with "physical Design Essentials" . Gud book surely you will get overall knowlege. There are
This is a very good book. Check this link
I am new to vhdl,i cant understand that why vhdl code is necessary .a circuit's operation can be recognised theoritically also.can anybody please explain me its uses and its importance
i am working on a project about implementation lte physical layer, i want to understand rate dematching,can any body help me
1) what is a net & wire, what is the difference betwee them 2) what pin, port, terminal and difference between them These terms confuse b/w verilog/vhdl implementatin and physical design i am not sure about verrlog implementation but net is logical naming of a connection b/w two pins, port is the hierarchical connection b/w logica
Please have a look on LTE PHY Lab, which is comprehensive implementation of LTE Rel.8 physical layer as a form of Matlab Toolbox. Here is the link: LTE PHY Lab? | IS-Wireless or on the matlab webpage: 3Pty - LTE P
hi I'm working on IEEE802.16 physical layer and I need to implement a Reed-Solomon codec in verilog ,I have implemented the encoder successfully but the problem is decoder,till now I have completed the implementation of syndrome calculator but I have problem in Massey-Berlekam algorithm implementation , and also its concept any document (...)