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148 Threads found on Physical Synthesis
Is there any way to make these 2 transition times equal? Post synthesis simulation just present electric behaviour in function of the physical specifications of the cells. There is no way to you interfere on its properties.
Hi, Suppose a given rtl had to be synthesized into a netlist ready for physical design. Assuming that the rtl contained only a I2C interface, what would be the approximate gate count of the netlist after synthesis ? Thanks, Aditya
Hello, I'm designing a simple circuit using Multi Supply Voltage. I'm using synopsys Dc Compiler for synthesys, therefore I must use UPF. For the physical implementation I will use Cadence encounter which doesn't support UPF, but requires a CPF. Since my design is simple (I have only one power mode) the translation from UPF to CPF is sim
Is it possible to use the physical placement or routing informations to optimize a netlist by back annotating the placement and routing information to the synthesis tool and resynthesize the netlist?? In other words, whether the optimization using the physical informations from the PnR tool can be used only for the PnR tool?
Hi, I am avanthi, M.Tech fresher in VLSI domain. I am good at RTL coding in verilog, verification, have hands on experience on synthesis, physical design, spice. I am in search of jobs. Please recommend some vlsi job consultancies in Hyderabad/Bangalore. Thank you
1. report_qor (synopsys DC) - to see overall statistics of setup WNS/TNS. 2. report_timing - to see setup slack of the defined path. 3. report_power - if power is the important goal. 4. if you did physical synthesis (DC topo) - see congestion report, maybe you will need to change floorplan.
You don't consider that 'x' is no physical signal state and can't be represented in hardware. What are you trying to achieve? Input signals can be either '0' or '1', nothing else.
We are hiring physical Design & STA synthesis Lead for India (Bangalore) with 5 -10 Years of exp. Also, we multiple onsite (Singapore/Taiwan) requirements for PD/STA engineers with minimum 3+ years experience. Wonderful Opportunity as we are one of the fastest chip design Services Company, Awesome Work Culture, One of the Top Pay master in t
1. from synthesis to gds, what are the must and should checks at each and every steps, like after synthesis, floorplan, powerplan, placement, CTS, routing.? 2). what are the inputs for the above steps?
Hi guys, I'm doing full flow (logical and physical) synthesis with Magma Talus. My design contains some memories which are considered as hard macros. The memory LEF files have been imported in library preparation phase. After PnR, I can see the memories on design layout. But cannot see theirs location info on exported DEF file. Why's th
i'm new to physical design. i'm going to start a project in physical design. i dont know what are the initial checks have to do. please can any of help me.. thank you.
Hi All, I wanted info regarding physical Design Engg jobs in Singapore. I have gone under training for 8months on the topics of Scripting, synthesis, Floorplan, Placement, STA, CTS etc. I have idea about tools like Synopsys - PT, encounter ,RC,Olympus tools. Will be there any opportunities in Singapore? Is there any medium to get job in Sing
Hello !! I have some std cells with the following pins : vdd, vnw, vss, vpw. FRAM views .lib Then, I have some other cells with the following pins : vdd, vdds, gnd, gnds. FRAM views and .lib I would like to make the synthesis and the P&R with ICC version : G-2012.06-SP4/bin/icc_shell Is it possible to use a mapping file ? or do I have to
The result (timing and placement) of physical synthesis, will be more closer to the final layout result as we take the placement and cell's physical attribute information from the layout team in advance through DEF file and use it during DC synthesis. physical synthesis is more advantageous (...)
Yes, thank you.... i worked on USB 3.0 physical layer design and UART.. But this is entirely different design what i doing now... If you have any materials for complex design pls give me... like design guide,,,, I go through many PDFs no were i found what i wanted....
I'm running a synthesis using RTL Compiler and I need a captbl file for physical synthesis for the interconnect RC extraction models. I can find .ict files but I don't have a .captbl file. How can I create one of these or which software do I use?
Hi, When I perform the logic synthesis in rtl compiler it deletes some "unused" bits, thats ok, I perform the post logical synthesis simulation and the results are still ok. I tell the compiler not to perform the optimization and maintain the bits and the simulation is still OK. My problem is when I perform the simulation after (...)
logic synthesis is to transform RTL code into gate netlist. physical synthesis is to take account the flooplan during the synthesis to improve the drive of the std.
R u interested in VLSI physical desigin ? so i can support u,on what i am working with?
hello every one can any one clarify HFNS? Thanks in advance RGR