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Pipeline Adc Comparator Offset

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12 Threads found on edaboard.com: Pipeline Adc Comparator Offset
Hi, pipeline digital correction solves some offset of comparator, but it can't correct gain error, right? For example, for a 10 bit adc, the first stage is 1.5 bit stage, the idea gain of this stage should be 2, but the actual gain is 1.9. Even with the help of digital correction, it can not correct the gain error? (...)
Hello all; In pipeline adcs where charge distribution dynamic comparators are used, the design of the different comparators is the same, they are only fed with different references to make them get exercised at different input voltage values.....When applying a ramp to the adc each (...)
I understand that digital error correction for a pipeline adc which is based on 1.5 bit per stage is used in order to correct offsets from comparator, opamp, etc. My question is, how does it actually correct this offset? What is the exact mechanism that allows you to be able to tolerate a larger (...)
our project is to design a 14bit 80M pipeline adc.The first stage is 4bit(1 bit redundancy) followed by 8 stages of 1.5bit/stage.the decision level of 1.5bit/stage is ?Vref/4,which can tolerated ?Vref/4(or ?Vref/2) offset.I dont know how people think up this method. and i dont know what are the first stage decision levels either. Could (...)
Hi, there, As is well known, the comparators in the sub-adcs of a 1.5b/stage pipeline adc can tolerate offset error as large as Vref/4, but why is it that ? can someone explain in more detail or post some links here, thanks! Added after 16 minutes: AND I also want to know which is the FIRST paper
Hi guys, I have a question with regards to the parameters such as comparator offset, gain, capacitor mismatch etc.. in a given stage of pipeline adc. In general how much variation can you expect for the above paramters in terms of percentage with increase or decrease in temperature and ageing for 0.18um technology. Assume (...)
Hi guys, I would like to know how to make each stage of pipeline behave similarily as close to each other as possible. I mean the multiplication factor of residue in each stage should be nearly same among all stage of pipeline. Its doesnt matter if there are large errors in each stage but the error factors like the comparator (...)
high speed adc 1. pipeline 2. fold 3. flash 300MHz flash A/D can use "switch comparator" use switch Cap .. and clock will do auto zero (cancel offset ...) comparator use "preamp + latch " for high speed signal you cn find many paper talk about this A/D
hi,guys I am confused that why makes addtion of alll stages' digital output can correct the error such as comparator's offset introduced. Expecting your comments, thank you very much. san
Dear all: I designed a switch-capacitor comparator,which is used in the pipeline adc. The function of this comparator is right,.but i don't know how to simulate the offset of this comparator. This comparator is Preamplifer+latch with autozero function.Thanks
im not quite sure abt all this testbed(cct) for testing pipeline adc performance such INL,DNL,SNDR & FFT using Cadence. Do anyone have some testbench cct for these performance metrics ? i knw it need to be done in transient.. but how about testbed signals ???
Hi fellows This thread interests me very much.. since my final school project it's projecting adc pipeline (with Flash arquitecture) i want to know if you fellows can give a clue how i can make the digital correction algorithm when i'm joining diferent types of arquitecture, i.e i want to project a pipeline that have more than one (...)