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Pipeline And Adc And Offset

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8 Threads found on edaboard.com: Pipeline And Adc And Offset
our project is to design a 14bit 80M pipeline adc.The first stage is 4bit(1 bit redundancy) followed by 8 stages of 1.5bit/stage.the decision level of 1.5bit/stage is ?Vref/4,which can tolerated ?Vref/4(or ?Vref/2) offset.I dont know how people think up this method. and i dont know what are the first stage (...)
Hi, there, As is well known, the comparators in the sub-adcs of a 1.5b/stage pipeline adc can tolerate offset error as large as Vref/4, but why is it that ? can someone explain in more detail or post some links here, thanks! Added after 16 minutes: and I also want to know (...)
Hi guys, I have a question with regards to the parameters such as comparator offset, gain, capacitor mismatch etc.. in a given stage of pipeline adc. In general how much variation can you expect for the above paramters in terms of percentage with increase or decrease in temperature and ageing for 0.18um (...)
Hi Yes, offset can be very important. for example gain error can be appeared as offset and has very important effect on total error in pipeline adc. regards
high speed adc 1. pipeline 2. fold 3. flash 300MHz flash A/D can use "switch comparator" use switch Cap .. and clock will do auto zero (cancel offset ...) comparator use "preamp + latch " for high speed signal you cn find many paper talk about this A/D
Hi, This is regarding the offset error of a pipeline adc (9 bits) with sign bit. Generally offset shifts the entire output transfer curve, hence doesn't change the shape of it and also the code width. I have few questions: 1). Is there any upper limit for the (...)
im not quite sure abt all this testbed(cct) for testing pipeline adc performance such INL,DNL,SNDR & FFT using Cadence. Do anyone have some testbench cct for these performance metrics ? i knw it need to be done in transient.. but how about testbed signals ???
Hi all In the sample and hold stage of a 1.5 bit pipeline adc converter, when i get the Vin-Vout characteristic of the stage (the one with the triangles), i have noticed that the whole characteristic is shifted up by 60mV. I suppose that this is the systematic offset error which is not so critical (...)