Search Engine www.edaboard.com

Pll Divider Verilog

Add Question

7 Threads found on edaboard.com: Pll Divider Verilog
Hi, * pll * (integer) frequency divider * NCO Each one has its benefits and drawbacks. Besides min and max frequency you need to know: * allowed jitter * frequency resolution * effort of implementation * do you need a certain (fixed or variable) duty cycle * how and how fast do you want to change frequency? Klaus
In general - you should use a pll for such a division ratio . Instead of trying to divide it with logic.
i want to divide the frequency which is 400 and 420 MHZ by 40 and 42 respectively to acheive lock in pll.input reference frequency is 10MHz.the purpose is to use the pll as BFSK. need help with designing the divider for n=40 and 42.can anybody send me sample verilog a codes for such dividers
hi i want to design a pll for three bands to get lock to the three differnt bands i have to get the divide ration as 64 to 148 for that i am using the dual modulas counters with prescalar 8/9 program counter as 5 bit counter and swallow counter as 3 bit counter can any body give the architecture for the above counter especially 5 bit synnc
yeah , u can use a beavioral models for the divider to speed up the simulation , i have seen the ADMS simulator of mentor , reduce the time of the pll simulation very mch by using verilog model of the divider khouly
hspice and spectre can simulate the pll system on transistor level ,though it is very slow but it is only a accurate method. verilog-A only simulate pll on behavior level and be used in simple research or verification in advance. It puzzle the IC design engineer to simulate pll in sample and fast method. Regards!:D
Use pll to double the clock frequency. Then divide it by 3.