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112 Threads found on edaboard.com: Positive Phase
A PI error amplifier would be my first guess. You didn't tell about the phase shifter range. Generally, an additional comparator for positive or negative phase difference and phase reversal switch are required to push the phase difference to the right part of the detector curve.
Hello, Please, I would like to know how the IR21362 chip handles the 3 phase pwm signals from microcontroller to determine the positive and negative half-cycles of each phase. I have pulled my hairs trying to figure that from the Microchip AN843 app note. I understand clearly from code, how the positive half-cycle of (...)
Theoretically, it would be sufficient to have the poles directly on the axis (zero real part) - and to start oscillations externally. However, in reality this is impossible because this would require zero tolerance of all parts. Therefore, taking tolerances into account and to ensure a safe start of oscillations the oscillator design always starts
I am allowed to enter only one input port on the LSSP window in Cadence Virtuoso when I actually have two ports at the input (one for positive terminal and other one for negative terminal which as a phase difference of 180 with respect to the positive terminal).LSSP in Cadence ADE simply invoke two one-tone-PSS(Shootin
High frequency phase shifts in an amplifier or opamp cause it to oscillate at a high frequency when negative feedback is added because then the high frequencies produce positive feedback. So the compensation capacitor is added at the VAS stage to cut gain at high frequencies so that the gain is less than one at frequencies where it would oscillate.
A DLL corrects the output (lead and lag) so that the output is in phase with the frequency. I understand how a positive delay can be created to correct for a lag in the DLL. A simple buffer can create a positive delay. But the minimum delay possible is 0 when there is no delay element. How does a DLL correct for a (...)
What is SDR and DDR here SDR - Single Data Rate (at single edge) DDR - Double Data Rate (at both positive & negative edge) 119792
1 st order are inherently stable but noisy 2nd order are less noisy and C2/C1 ratio affects pole position 3rd order are inherently unstable with >180 deg phase shift and negative feedback becomes positive feedback. Rule of Thumb ratios help provide LPF additional rolloff using lag-lead filters to give phase margin at unity gain and (...)
Common base amplifiers are non-inverting and this one uses a capacitance divider feedback to the emitter for positive feedback at LC tank resonance with 0 deg phase shift. Thus oscillation is sustained when the loop has gain at resonance by ratio of Collector to emitter impedance at resonance. The Bias resistors control the dc current operati
Hello Members, I have a following circuit designed in Schematic window of ADS. I would like to export the design to ADS Layout window for fabrication phase. Can someone kindly assist me. Awaiting your positive replies, Circuit: 118215 Regards
All the above is right (except for a missing pair of parenthesis for (Zin-Zs) in post #2), but the essential concept should be emphasized: The reflection coefficient is the ratio reflected_wave/incident_wave. Both waves are complex magnitudes (phasors). Its modulus is the ratio of amplitudes (real and positive). Its phase can be viewed as the ang
Oscillators are a combination of positive feedback for Barkhausen condition and negative feedback for DC bias to get into the previous condition of AC phase shifted by 360 deg & Av>=1 condition. Noise is inevitable as is any slewing DC. Which do you think applies to the lack of oscillation? Hint: much more details are need this side to help any
Hi everyone, I'm developing a system that store the voice recorded by a microphone into a SD card trough a microcontroller. I would ask a question about the conditioning circuit for the microphone. I set the voltage reference of microcontroller's ADC at 3.3 V and 0 V for high and low voltage reference respectively. The microhpone is a preamplified
Hello Friends My project is all about self checking luts using sedc technique. In this phase am suppose to inject faults into lut and use sedc scheme to detect it.. Am trying to to it in altera cyclone 2 boards or psoc device..can any one help me out. Hope for a positive response Happy day
An oscillator needs positive feedback. If it has only negative feedback then it is an amplifier, not an oscillator. The phase shift circuit in an oscillator has a certain amount of signal loss which must be made up by the gain of the circuit. A simulator does not know that noise is amplified and gets an oscillator to start oscillating. Then you mu
The lock detector is shifted in phase to produce max voltage when synchronous , whereas the loop detector is at mid-scale voltage giving negative feedback on phase error at all times within the constraints. Since the lock detector peaks when locked, the feedback would be either positive or negative making the loop unstable. There are many (...)
The 2200pF capacitance of the piezo transducer causes phase shift at the output of an opamp. The phase shift causes the opamp to oscillate at a high frequency, maybe 1MHz since the negative feedback shifts to become positive feedback. You can add a pair of comlementary emitter-follower transistors to the output of an opamp for it to drive (...)
The three RC phase shift parts create a total of 180 degrees of phase shift which is used for positive feedback and the inverting transistor causes the remaining needed 180 degrees of phase shift. The phase shift parts cause an attenuation of about 29 times. The voltage gain of a single transistor (...)
Are you sure about that 0V? I have just read the data sheet and although I did not find anything pointing to it I do for some reason mistrust that the 0V spec, or it might have been the LT3081 that only gave 0V under certain load situations that made it in many cases not true. The problem is that LT3083 only goes up to 23V, I had remembered othe
The impulse response plot is correct, but not showing the positive impulse at t=0. I think the step response shows better what happens.
The transistor is a "common-base" amplifier. Its collector feeds positive feedback to its emitter through C2. Some websites call the oscillator a "Colpitts" type.
The FFT decomposes the signal in frequency, generating a complex spectrum with both positive and negative frequencies, depending on both amplitude and phase relationships. We are now not interested in the phase. Fixing a frequency, the absolute amplitude for positive frequency is the same of that in the negative part. So, (...)
I presume it's a pseudo-differential ADC input that requires positive common mode voltage on the differential pins. So additional biasing circuits are needed. Preferably buffer amplifiers should be used. You also didn't tell if you want to measure the instantaneous input voltage with respective fast sample rate or use an analog circuit to conve
in folded cascode compensation capacitor and load capacitor is you must use positive fedback gain cause high unity gain frequency and nice phase Margine. - - - Updated - - - if you want increase the campensation capacitor,unity gain will be decrease.
i know for stability we need positive PM GM . that means at -180 degree gain should be negative(in decibels) for stable systems . From where this arrives i mean why -180 ?? i read somewhere that after -180 degree NEGATIVE FEEDBACK BECOMES positive FEEDBACK and if at that time gain >1 than system will oscillate and become unstable ?? why negative b
Can a negative-feedback system ever have large positive phase shifts that causes instability? All the examples in my old textbooks deal with instances where the overall phase shift approaches -180°. How do we deal with instances of positive phase shifts near and beyond +180°? I found this reference (...)
i faced some problems when i try to implement the pll block in simulink model. so, i need help. My confusions are: 1. How can i estimate positive sequence voltage from 3 phase unbalance voltage source? 2.how can i simulate pll circuit? THANK YOU.
please leave this figure it is not that clear, refer to the first one of my post with the separated results , the curve with the DC gain of 81 is the circuit with the positive feedback the second graph with the DC gain of 74 is without the positive feedback I dont know what you mean to say by my self, I am using mentor gr
Hi, In case of negative phase difference, it is understood that the output lags the input by the phase difference. But what is meant by positive phase difference (Ex. High pass filter)? Is it that output leads the input by that amount? If so, how can the output be there before the input?? Thank you. OK- let`s take a
Yes noise can make your circuit unstable. As you must be knowing thermal noise is wideband. The high frequency noise components will excite your loop. If there is insufficient phase margin, then the loop will not behave properly. If the phase margin is negative, then your loop goes into positive feedback.
? if some one can throw some light on the issue of negative feedback on the positive terminal of the would be helpful The lower transistor (original drawing!) - together with the resistor - operates in common emitter configuration. Thus, there is a phase inversion between its base (opamp output) and the ba
You'll determine stability by analyzing the loop gain magnitude and phase characteristic. For the simple case of monotone magnitude characteristic, a positive phase margin implies stability. A considerably larger phase margin will be required for acceptable time domain behaviour, however. Strictly speaking, an OP with (...)
Why are we using positive feedback for low-pass and high-pass filter?
hi please , when i simulate patch antenna , i find s11 for desirable frequency (fr) <-10dB (good adaptation) , but i find phase diagram of s11 positive and always >0 deg! what that means please (physically) and is there an error §?
AC energy meter entirely different from dc power measuring. Energy Metering IC with Integrated or and positive Power Accumulation ADE7768
Hi; Differential signalling there are two signal traces (ie clk_positive and clk_negative, they are inverted/180deg phase shifted each other), receiver end use a differential amplifier to recover signal. In this system positive signal reference is negative signal. In common mode, you have one signal and a common signal which is ground and (...)
See the schematic attached. Since the amplifier is having a a negative gain at dc, I am expecting the real part of my input impedance as positive,through miller approximation. But cadence simulation gives a negative value for the real part of input resistance(or it gives a phase of 180 degrees at dc) Wy so?75172
There is a spurious resonance @ 9KHz with 25dB gain above normal at that point, so negative feedback becomes positive when Gain>1 & phase Margin=0 what are the switching rates of SMPS1, SMPS2 and also Load if known.? Pre-load may be necessary as well as lower ESR caps as suggested above on inputs of this loop {SMPS2}. > increased storage on
The (+) input of the opamp is biased at 0V so an AC input that swings negative and positive will cause the opamp to act like a rectifier if the negative voltage does not destroy its input transistor.
Hello, You can describe every sinusoidal signal based on V(t) = A*cos(w*t+phi). At t = 0 the phasor (vector) describing the signal has length of A and has positive angle (w.r.t. x axis) of phi degrees. It rotates with omega (w) radians/s You can decompose the phasor in its x (In-phase) component and y (quadrature) component. Icomp = A
When I saw this for the first time (many years ago), I thought the letters RST meant RESET. But I could not figure out why there were three terminals :-) Maybe the first was the positive, second the negative and third was a spare :-( This is almost like looking for a triangular package for an opamp ...
Hi Palmeiras, to 1): No, it is not correct; the phase shift will be frequency dependent to 2): Yes, correct to 3): No, in will not oscillate due to 360 deg phase shift for dc. As a consequence, there is a so called "latch-up" effect. You can observe a similar behaviour for each opamp with a positive resistive feedback that exceeds negative (...)
Analog solution: A phase detector with a 50% PWM reference signal, low pass filter plus VCO without feedback, and a VDD/2 comparator for the filter output signal to get the direction signal. Some positive comparator feedback to achieve a reasonable stop band.
What i guess is, due to the gain margin is positive, thus the system auto change to -540 so the gain margin will be negative? Does this make sense? No, as I told you: The phase response looks strange. Check your simulation setup. I suppose, you have shown the loop gain - correct?
i need a verilog code for phase detector to detect a positive edge of two clocks i.e one fast clock signal and one slow clock signal, simultaneously and produce output as just a single pulse..i need it soon..pls help out.
VNA's can measure the phase (in +/- 180 degrees range), introduced by a transmission medium. phase values could be negative at some frequencies and positive at others, depending on the initial phase value and the nature of the transmission line. To measure the phase difference between two RF signals you (...)
Consider the following transfer function (voltage out divided by voltage in) of a circuit: (s-1)/(2s+1) The question was posed in our engineering class, at what frequency does the gain equal zero? Zero here means for an input signal of a given frequency there is no signal at the output, ie. we are not talking about 0 dB. I am of the opinio
Agree with Braski. Generally you talk about phase margin when your feedback loop reaches a gain of zero. You want to maintain some positive phase margin at that point, such that you have "room to push/pull" in your feedback loop.
Hi, I am simulating the AC response of a unity-gain feedback amplifier using Spectre stb analysis. It works fine for most corners. But for some corners such as slow-fast(t=-40,125; vdda=2.05), the loop phase suddenly change to 0 degree at DC (it's supposed to be 180 degree). That means positive feedback! It's so werid. Is it a problem of spectre
Hi all I have problem design 2 stage fully diff opamp with sc cmfb. I am using 0.18um from tsmc process. When I run w/o sc cmfb the gain about 65db, phase margin 64 degree and GBW~540Mhz. If sc cmfb is connected the gain a little bit reduce to ~60db but outputs from negative and positive have diff result for GBW and phase margin and GBW (...)


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