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112 Threads found on edaboard.com: Positive Phase
A PI error amplifier would be my first guess. You didn't tell about the phase shifter range. Generally, an additional comparator for positive or negative phase difference and phase reversal switch are required to push the phase difference to the right part of the detector curve.
Hello, Please, I would like to know how the IR21362 chip handles the 3 phase pwm signals from microcontroller to determine the positive and negative half-cycles of each phase. I have pulled my hairs trying to figure that from the Microchip AN843 app note. I understand clearly from code, how the positive half-cycle of (...)
Theoretically, it would be sufficient to have the poles directly on the axis (zero real part) - and to start oscillations externally. However, in reality this is impossible because this would require zero tolerance of all parts. Therefore, taking tolerances into account and to ensure a safe start of oscillations the oscillator design always starts
I am trying to figure out the s-parameters of a push pull class B power amplifier, but the problem is that the input is differential. I am allowed to enter only one input port on the LSSP window in Cadence Virtuoso when I actually have two ports at the input (one for positive terminal and other one for negative terminal which as a phase difference
High frequency phase shifts in an amplifier or opamp cause it to oscillate at a high frequency when negative feedback is added because then the high frequencies produce positive feedback. So the compensation capacitor is added at the VAS stage to cut gain at high frequencies so that the gain is less than one at frequencies where it would oscillate.
A DLL corrects the output (lead and lag) so that the output is in phase with the frequency. I understand how a positive delay can be created to correct for a lag in the DLL. A simple buffer can create a positive delay. But the minimum delay possible is 0 when there is no delay element. How does a DLL correct for a (...)
What is SDR and DDR here SDR - Single Data Rate (at single edge) DDR - Double Data Rate (at both positive & negative edge) 119792
1 st order are inherently stable but noisy 2nd order are less noisy and C2/C1 ratio affects pole position 3rd order are inherently unstable with >180 deg phase shift and negative feedback becomes positive feedback. Rule of Thumb ratios help provide LPF additional rolloff using lag-lead filters to give phase margin at unity gain and (...)
Common base amplifiers are non-inverting and this one uses a capacitance divider feedback to the emitter for positive feedback at LC tank resonance with 0 deg phase shift. Thus oscillation is sustained when the loop has gain at resonance by ratio of Collector to emitter impedance at resonance. The Bias resistors control the dc current operati
Hello Members, I have a following circuit designed in Schematic window of ADS. I would like to export the design to ADS Layout window for fabrication phase. Can someone kindly assist me. Awaiting your positive replies, Circuit: 118215 Regards
A reflection coefficient (Г) of 0 means that all power is absorbed by load. This happens when both source and load impedance are equal. A reflection coefficient (Г) of 1 means that all power is reflected by load. This happens if the load is open circuit. What does a complex value of reflection coefficient mean? I do understand t
Oscillators are a combination of positive feedback for Barkhausen condition and negative feedback for DC bias to get into the previous condition of AC phase shifted by 360 deg & Av>=1 condition. Noise is inevitable as is any slewing DC. Which do you think applies to the lack of oscillation? Hint: much more details are need this side to help any
It will probably oscillate.... The output is never connected to positive input directly otherwise phase will be 0 degree and feedback loop gain will be more than one and it will start to sing...
Hello Friends My project is all about self checking luts using sedc technique. In this phase am suppose to inject faults into lut and use sedc scheme to detect it.. Am trying to to it in altera cyclone 2 boards or psoc device..can any one help me out. Hope for a positive response Happy day
An oscillator needs positive feedback. If it has only negative feedback then it is an amplifier, not an oscillator. The phase shift circuit in an oscillator has a certain amount of signal loss which must be made up by the gain of the circuit. A simulator does not know that noise is amplified and gets an oscillator to start oscillating. Then you mu
The lock detector is shifted in phase to produce max voltage when synchronous , whereas the loop detector is at mid-scale voltage giving negative feedback on phase error at all times within the constraints. Since the lock detector peaks when locked, the feedback would be either positive or negative making the loop unstable. There are many (...)
The 2200pF capacitance of the piezo transducer causes phase shift at the output of an opamp. The phase shift causes the opamp to oscillate at a high frequency, maybe 1MHz since the negative feedback shifts to become positive feedback. You can add a pair of comlementary emitter-follower transistors to the output of an opamp for it to drive (...)
The three RC phase shift parts create a total of 180 degrees of phase shift which is used for positive feedback and the inverting transistor causes the remaining needed 180 degrees of phase shift. The phase shift parts cause an attenuation of about 29 times. The voltage gain of a single transistor (...)
a Split rail with an option to track or control independently is useful. The efficient way is of course to use SMPS with a single rectified DC source perhaps with phase control and a dual SMPS converter one positive and one negative. The transformers will therefore operate at the switch rate and not 50/60Hz.
The impulse response plot is correct, but not showing the positive impulse at t=0. I think the step response shows better what happens.