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S. the attached file in this post!
hello, what is the relation ship with the POT ? post un shematic to comment your question ... Anode cathode of backlight led ?
Can you post the complete code for the system?
Hi zam_nmn, I'm afraid I don't know anything about that type of filter. If you post images if the fields though, I can tell you if they are correct for your setup or if there is an error somewhere.
Hi. This is my first post on EDA forum. I am currently doing unit delay gate-level simulations. I see lot of glitch power in my design. In order to trace the glitch, I would like to count the number of gates through which the glitch propagates until it hits a sequential and stops. Is there a way to get this count during vcs simulation or I can see
You really need to be more clear. You havent shown the type declaration for this matrix. You havent shown the base type for each array element. So, please, post some code, and we can comment more.
post your schematic - - - Updated - - - ADCSRA=0x85; //ENABLE ADC, PRESCALER 128 That doesn't set the prescaler to 128 but 32 ADMUX=0x00; //PC0, AVcc AS REFERENCE VOLTAGE Also a misleading comment, this sets the Vref to the voltage connected to AREF I don't see anywher
You simulation appears to be in error. Since I don't know how you simulated it I can't comment on what the error might be. Can you post your simulation circuit and the results? Do you mean the current "through" R3 is always 0 in the simulation?
First comment, you need to learn how to post code at ebaboard. It's really annoying to read it as a blurred screen shot.... Secondly, please consider on your own what you want to achieve hardware-wise. There are cases where a common logic design is used for product variants with different functionality, controlled by a configuration pin. You
As an additional comment, the circuit in post #1 misses a resistor to set the negative resistance value.
hello, in your post #1 , how do you want to send somewhat with a comment in front of your function. and add some delay between invoice.. void main() { init(); //now you want to send something, so first load a string into the sendBuffer while(1) { sendUartString("helloworld"
post your circuit here then the people will comment on it..
no I am doing all exactly the same as post #47, but all in multi-blocks You are doing not the same. Previously, your counter has been counting 0,1,2 ... 7, 8, 0 ,1 now it's 0,1,2 ... 7, 0 ,1 That's a result of the asynchronous reset on counter_8clk = "1000". But the full truth is, you had already asynchronous resets by
The comment in post #1 suggests that the intention is to evaluate the effect of varying OP offset voltages in simulation. We'll usually want to find the worst case output respectively input referred offset voltage.
Generally the simulator uses more complex and accurate equations to determine the circuit operation so it is likely more accurate than your hand calculation. If you post your results for both I can perhaps comment further.
The arduino is a controller board. As far as I know there is not 2.4 GHz communications circuitry on it. Are you using a arduino that DOES have a wireless communications portion on board? If so , post us a link to the board info, and we can comment on it.
As a delayed comment on the post #13 testbench, besides possible problems in the corrected DUT code that hasn't been shown, the testbench misses to assert the reset signal. So unless the DUT uses an initializing statement, the accumulator register will be never reset. P.S.: is this correct in vhdl Clearly no. Please observe
2. I'm not aware of any, to elaborate my comment in post #6. 1. A >500k series resistor limiting the OP input current, bypassed with a capacitor to reduce resistor noise.
Hi, You need to post your code, either use the # tags to insert the code or zip it.
Hi, I'm running post layout simulation with cadence and I'm getting this error: ERROR (SFE-23): "input.scs" 63: re1 is an instance of an unidentified model M2. I tried in two ways: First, I ran QRC for R and C and, second I ran just for C. The first time I got this error but the second time no errors and post layout simulation was done succe
First comment, the second waveform in your initial post is wrong, because the signal is undefined for half of the period. You may think of this point as a trivial drawing error. But it's also symptomatical for not considering the properties of the signals involved in the problem. But in this example, Fourier did not determine the freq
Hi roki, Please read again Eriks comment in post#4: "In your 1st sketch you showed an inverting pMOS, in your 2nd figure there's a non-inverting NMOS source follower. " The rule is as follows: The dc gain within the loop must be negativ (1 or 3 or 5 phase inversions). If the FET inverts (common source) the opamp must NOT invert and vice ver
Your post is missing any information for detail help with your questions. Regarding voltage references, you'll possibly remember my previous comment that Pt100 measurment is essentially ratiometric and doesn't need a stable voltage reference, if Pt100 circuit and ADC are using the same reference voltage. Apparently, you didn't yet think about th
I can help you... But I am not familiar with the registers.. can you comment the code? ---------- post added at 03:10 ---------- Previous post was at 02:54 ---------- check page 91 -- interrupt section ---------- post
Putting a voltage directly across an inductor will make the current rise at a rate of dI/dt = V/L. The resistance will limit the current and add some voltage drop. Normally you would try to minimise its effect if possible. Zero resistance doesn't actually cause a problem. I cannot see a zener so cannot comment. Maybe if you post your circuit &
I guess you noticed, that using an OP error amplifier for the constant current path promises a more exact current regulation than the simple Vbe based current limiter form your initial post. Looking at the schematic in post #9 demands a comment that dynamic behaviour of both current and voltage regulation, as well as the transition between (...)
If you post the paper which you have mentioned above and simulation results, we can comment about the subject.
I didn't hear a question from the original post. To add a comment on my own, adding a bias current seems reasonable, you are achieving this basically by defining the circuit on the primary (transistor) side.
You post screenshot of config setting page of G840 software. Actually i have also got genius programmer but it is G540. I am posting from mine. Most likely yours may be similar. Advance members may comment more [url=http
can you go for L293D or L298.. it will be simple for you.... if you want 74ls series then post the circuit so that we can comment.....
Sorry, none of Ansof product runs on Linux. Your best bet is in the previous reply. Regards ---------- post added at 13:57 ---------- Previous post was at 13:33 ---------- Please ignore my previous comment, I was wrong, they do support SuSE and RedHut 64 bit. Regards
tell what you have done till now.see... post your code and circuits for us to see and comment...........
Thanks Guys for your valuable posts. As I mentioned earlier, I have created schematic design. And now I wanted to convert it in to the PCB design. So the main problem infront of me is, I am using Zuken product first time in my life. So I am not atall aware of it's basic flow. I am facing defficulties in the following things 1. I have done with
you can also post the error you are getting along with the error number....
I assume you want help to write the software. The first step is to draw a flow chart. So I suggest that you do this and post it so we can comment. No-one is likely to do it for you. We are here to help, not to do other people's work for them.
Hi There, I may be too late answering this post but I'll comment anyhow, in case other readers view this post and can benefit from my reply. So I'm assuming you are looking for the Datasheets of the Pittman motors in order to repair a damaged motor or order the replacement parts required. The Pittman brand Motors used on the Scorbots were (...)
Can you zip and post it here includes your DSN files ? :)
any comment on differential and single ended IO query (asked in the previous post of mine). review my previous answer They can always be used single ended.
Hello, maybe you can post a graph and some requirements for the antenna to enable others to comment also.
I regularly access and recently he has included a new player in his site. It is xcellent to use and i have a small question in it There is a comments section in which if i enter i comment, it automatically shows d location from which post is done. For example, if im 4m hyderbad it shows d same...... how is dis possi
Yeah! quite easy to understand, but did you check the PAR details?....Try coding all in one process and check the results with this!...I doubt that this way of coding in multiple process and sharing signals may create some routing or performance issues!....Check PAR results and post here...Let us see
I've tried for the va1, but it doesn't works. I attached here the code. Hi DoraSzasz, any ASM code not appear in your post. Can you re-attached the TASM codes regards bassa
Hi there can you post the details how you solve the square lattice problem using CST ? regards
Please, post (some) schematic, bode plots and transient response
Well what have you tried so far? Why don't you post the code you've written so far, and people can comment. If somebody just writes the code for you, then you won't learn much will ya?
Designing a switching transformer is not a trivial task. Can you post your schematic, so I can comment?
Hi, I might help if you can post your .bashrc file here. I am not sure but it seems like some paths are missing in your .bashrc file.
Hello fredflinstone. Thx for ur comment . I am doing the post parasitic block level simulation now . As for the comparator its a sort of inverter type comparator .Attached is the schematic . Can u give some idea/paper to proper run test on it ? Thx in advance .......
post your code. Without that it is not possible to comment on what is wrong.
Thank you very much Zerox100! In the web I found only descriptions of how to use Dual-Clock FIFO megafunctions by altera, but I'd like to have VHDL code for that function, otherwise I can't really understand the behaviour of the model. If you could upload it or post a link, I'd be really pleased! Thank you a lot! Gert