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19 Threads found on edaboard.com: Post Layout Problems
Hi, please post your schematic, and your PCB layout. The code also could help. (My first assumption: PCB layout problems. Especially ground bounce. Is it a breadboard test?) Klaus
Hi, first: passed means passed. Therefore i see no need to change anything. Every change means a new approval. But I understand you want to improve on emissions. One point is to place an additional capacitor in parallel to the transzorb. If this really improves the emissions is hard to say. I mainly depends on PCB l
Hi all, i have designed a 920 MHz pierce oscillator using 1v vdd transistors included the 45 nm cadence gpdk045 tech. library . During the schematic simulations phase everything works fine. I did the layout and after post layout simulation using the extracted circuit, my circuit wont oscillate. to try to solve this problem, i added the (...)
If possible, post here the schematic circuit so that I can provide to you a more accurate answer. +++
Hi all: I'm facing a problem about the Calibre LVS/PEX, I will describe it using this simple current mirror shown below, X and Y are same MOSFETs with width=16, nfing=2, m=1: 101041 When I just do the layout with only one finger for both X and Y (w=16, nfing=1, m=1), and do the post-layout simulation, I injected 100
I have designed a front-end and now i want to layout it in cadence and post layout it using assura. but there is some problems in extracting extracted file at both of the LNA and mixer , all of transistors have the width fixed to 15u , capacitors to 30fF, all kind of resistors to 5.62k and inductors to a few hundred pH. I (...)
Hi, I have timing analysis problems for post-layout sta using primetime. This is the part of the report: Startpoint: .../ctrl_in_ack_rx_o_reg (rising edge-triggered flip-flop clocked by clk_i)
Hi, In pipelined ADC, I face degradation of SFDR and SNR in post layout simulations with the coupled capacitance extraction results. Mainly I see with the switched capacitor layout. It works fine with the decoupled capacitance extraction, but with couple extraction, SNR & SFDR drops by more than 25 dB. Can any one help what could be (...)
try your hands on the class assignment problems yourself. your other post "help on design rules. thank you :)" is also of the same type. if you have any doubts when you are trying yourself on the problems , you can get help by asking for specific difficulty.. suzysuzy make easyeasy of assignments!
looks like you have interference problems - can you post a photo of your layout and a full schematic?
For the most time, the timing report is correct, because it is not using the best case for calculation. But if you have problems,specifically timing related problem, then post layout simulation will help you possibly find those. But it is SLOW and tricky. Best regards, /Farhad Abdolian
Run postprocessor after the routing and finishing touches end. Open the postprocessor window and u'll have all layers defined there, ready for priniting.
Hi, I design an ic using an opamp cell from CDK, but the CDK can not do the post layout simulation including the opamp cell, my quetion is: 1. I don't want to design the opamp by myself, is there any problems for using the opamp cell from CDK? 2. what is the postlayout mainly for? I think it is for (...)
There could be thosands of reasons causing problems with your synthesizer. You do not say anything about the output frequency of the synthesizer, but intermittent failures caused by output mismatch seems unlikely. You have to give us more information. Please post circuit diagram, layout , tech data etc.
It is fine. When you do post-layout simulation with parasitics, there should be many nodes without DC paths such as dangling paths.
It may lead to assign statements in your final netlist which some back-end tools will not accept. This post: shows how to fix that problem. You can also get ruid of this by flattening/ungrouping the design
When I was designing a 60MHz 10bit Pipelined ADC, I found it tough to do a post layout simulation. The key difficulty is to get accurate FFT result. For SRAM, ROM or Flash post simulation, I was only care about the timing delay with tolerable error up to 10%, using StarSim or UltraSIM. However, for pipelined ADC with SC structure, if (...)
Yes, if you know something about converting pcad to orcad, orcad to pcad post your reply
As i described in a previous post now when placing pins, for example the invertor, I placed an IN, OUT vdd! and a gnd! I DRC and extract the design OK. Viewing the extracted layout the nmos transistor is the wrong was round. Now when when it comes to simulate I have to specify the IN the vdd! and gnd! however they are not under global nets but un