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115 Threads found on Power And Synthesis
I want to obtain power numbers from ptpx on an RTL based design. Gate level sims are not ready yet. Currently I have a RTL simulation pattern that I have converted to SAIF. This file is read into the synthesis flow to generate a SAIF_MAP file. I then read the SAIF_MAP and SAIF pattern files into ptpx to obtain an average (...)
hi everyone, i am using Xilinx 9.1 synthesizer to synthesis my design. i used Xpower Analyser option to find out power but it gives me the same power for any RTL i use. What is the reason and how to rectify it. ?
by design you could define a "master" clock gating, and add local clock gsating (in RTL or by synthesis tool) to reduce the power consumption. The idea is to place the clock gate as closest as possible of the clock source, to have the maximum of buffers after this clock gate to reduce the clock tree consumption. Then one master clock gate (...)
How to calculate the max current and typical current of a design while synthesizing the design? Is not it same as calulcating max power and typical power? How to ge that during synthesis in bothe the above cases. I know that report_power command in (...)
Hi All, I wonder if anyone would can share their FPGA reference flow or methodology scripts. Currently I'm looking at Altera's Quartus and would like to build a full design flow from compile (scripts going through different stages of synthesis, power checks, etc ) to finish. I think this should be already available somewhere (...)
Each instance of the the module can be implemented using different std.cells depends on timing/area/power requirments. So, one module can have different content after synthesis, but RTL had the same content. Uniquify makes copies for each instance of the module and make it possible to change module content independently.
Hi every one I am calculating Area, power and timing in ASIC using Synopsys Design Compiler and ModelSim. After Anlyzing and elaborating the design then applying constraint and Compiling, I saved the sdf file (using Design Compiler) as follow: write_sdf ./SYNOPS/SOURCE/test_defult.sdf when I use (...)
some remarks: 1- large 40k? 2- how many scan clocks do you have? or do you ignore the jtag-flops from the scan? If you have only one scan clock domain, your design will synthesis fully synchronously, but your design requires to be simulate with two clock domains. 3- did you share the same power/ground lines between the analog and the (...)
There are three main constraints in ASIC synthesis Timing, Area and power. All these has trade-offs. If you wants better timing you may require large area and power. If you require small area your performance will effected.
hi folks, Iam trying my hand at power aware synthesis using synopsys upf flow. Here i will try to raise some doubts and share my experiences about this flow. Lets start with the most basic stuff create_power_domain command...iam unclear about importance of different scopes...can't we (...)
Hi all, I'd like to ask you about the possibility of editing in the leakage current value of the cost function used in the power optimization algorithms in synthesis tools?Is it possible to do? and what is the recommended tool for that?:-D Thanks a lot Best, Hamzah.
Hi all, I have a problem with the synthesis of leon3... I want to have the post-synthesis verilog to make simulation with modelsim, have the VCD and the SAIF, to use primetime for power report... everything is ok but some module's names are too long and I can't write the DDC and (...)
I'm not sure what the best power analysis "point" tool is but I can say that switching back and forth between different design tools working on different views is quite common in IC design. There just is no push button flow.
Critical path locates at a sub-block which occupies a seperate power domain. So I use hierarchical flow during synthesis. First, synthesize the sub-block with its own upf and write out subblock.ddc. Then during top synthesis, read top RTL and subblock.ddc, and propagate (...)
dear all i have vhdl code for vga interface, i did all process such as synthesis and implementation so i need to know how i can use Xpower to measure all power ( power by Voltage Supplies,power by User Logic Resources,Thermal Powe) wait your reply regards
Hi all, I've seen below thread: "thread23278" However, a couple of years passed since this thread has not been active. Every tool vendor is working hard to produce better tools, therefore I'm raising this question one more... For example we used powercentric of Azuro for our latest design and we've seen reduced power figures on clock (...)
the synthesis tool will choose for you the best flop for a path. if the path are less constraint, it could not choose the best one, but there isn't any impact on the design result. and Best means what? In power/timing/area domains?
Hello I'm runnign synthesis with Design Compiler. After differents synthesis my results in report timing, says that the slack is zero or negative. So my question is, because i'm looking for positive slack for a secondary power optimization, how can I see the positive slack?
I tried to import Verilog netlist into schematics (I use Cadence virtuoso), and it asks for an "attribute file" (by default it should have the same file name as the netlist file with .attx extension). I don't know what that file is, and the synthesis process does not seem to produce the file. I heard it may be the information of (...)
I am attempting to design a clock tree for a design with clock gating. I am having trouble understanding the syntax for the ctcsh. My design gates a clocks for power and functionality. In each case, devices clocked by the gated clock are expected to be synchronous with devices clocked by the ungated clock. Should I time through the (...)