Search Engine www.edaboard.com

Power And Synthesis

Add Question

115 Threads found on edaboard.com: Power And Synthesis
hi all, if i give the set of libraries operating at diff voltages say 1.8,1.2, and a level shifter library, and use insert_level shifter cmd and then compile do the synthesis tool itself divides the power domains and insert level shifters to satisfy the constraints or should i nee d to (...)
after u are done with synthesis and P&R , follow these steps 1) Do RC extraction ( Parasitic extraction) . for eg. Synopsys Star-RC ( or Cadence Assura) Tool will do it. It will generate spef files. 2) Run STA for Timing Analysis for eg. Synopsys Primetime Tool will do it. Input to it is your spef file and gate-level (...)
Hi, I am comparing a number of arithmetic adders based on their power consumption. I use Synopsys Design Compiler for synthesis and Prime Time PX for power analysis (using back annotated SAIF files, from simulation in ModelSim). I can't figure out if the Synopsys tools are actually analyzing the power (...)
Hi all mentors, I am in urgent need of your help as I need to present my project to the professor. I have written a code and synthesized using xilinx and the details are { family: spartan3E Device: XC3S100E package: VQ100 speed: -5 synthesis Tool: XST(VHDL/Verilog) Simulator: Modelsim-XE Verilog Preferred Language: (...)
Hi all, I am using the TSMC CMOS LOGIC 0.18um (3.3V) technology. I was wondering in which stage of the digital design flow would I have to mention about dual power supply (+/- 1.65 V). I am in the synthesis stage and the library I am using has a nominal voltage of 1.8 V for a tt process corner. There are no libraries with a nominal (...)
The constant 1'b0 or 1'b1 in HDL is realized with a wire connecting to VDD or GND. That is fine until you consider the ESD issue where a gate of a MOS FET is connecting directly to the power supply or ground. That's where the tie on/off gates come in. They are usually provided by the standard cell library and synthesis tool (...)
Hi Chunwei, If you calculated the coefficients as amplitudes, you have to square them in order to have the power ratios needed for synthesis of splitters. Check your array synthesis method in order to be sure that the coefficients are in magnitude (and eventually phase as well) and not in (...)
Hi, all, I have mips.v (register level verilog code) and a tcl script of design compiler. For applying clock gating, I add such a command set_clock_gating_style -minimum_bitwidth 2 in my script. but, after the synthesis, the power report is still the same as that without that command. Do you (...)
What is the main function of spyglass? Spyglass can be used to check the CDC(clock domain crossing), DFT rules and estimate the coverage, low power analysis and many more @ RTL level. This is very much useful to check all above things very early in the design cycle.
usually you can first synthesis with only the low Vt cells, then optimize it, it will replace some of the non-critical cells with high Vt cells so that it can reduce the leakage power, and meet the timing requirement at the same time.
Hello Sir/Madam, I run a design both in 400KHz and 1.1MHz clock constraint. For design constraint in 400kHz, total leakage power = 2.7uW For design constraint in 1.1MHz, total leakage power = 0.7 uW Can anyone help to explain this? THanks.
multiple gate offers choices for the synthesis tool. a mux can be implemented by and gates and inverters, but when a mux is present in the library, it will be efficient in terms of area, power, speed, as compared to a mux which is synthesized using and gate and inverters. Hence so many cells (...)
Dear all, In my design, total power consumption estimated after synthesis by Cadence-BuildGates is: Internal Cell + Leakage + Net = 0.2904 + 3.9775 + 0.3833 = 4.6512 mW While, after place-and-route, Cadence-Encounter reports: Total leakage power = 337395.002511uW Can anyone tell me why there may be such a (...)
Hi, 1- I don't know important of libraries in synthesis and What's different of libraries in synthesis?? 2- I need libraries for Leonardo-spectrum , please send me these. thanks. Refer to Library Compiler & Design Compiler & power Compiler for more details ... The simplest explaination is : Library i
Hi, I have several papers for you 1st one is "synthesis of a compound T-junction for a two-way splitter with arbitrary power ratio" 2nd one is "The modified stepped waveguide T-junctions and the method of initial design" 3rd paper is "Design of unequal H-plane waveguide-power dividers for array applications" at
its for varying the voltage output or say modifying the voltage wf acc to ur application read any power elect book for that or google for more
.lib file contains the following all parameter units like area, time power...(in um, ns, nw) the timing and power information of the different gates. wire load model(like 10x10, 20x20...) operating conditions(PVT) these information is used in the synthesis process using library compiler .lib fiile is converted into (...)
Hi deepavlsi, Oh my, you've broken nearly every synthesis rule in the book! In addition to FvM's suggestions, try this: module top (clk, start, x, y, result, done); input clk; // we will do one multiply per clock input start; // begin the calculation input x; // input valu
hi, i need to calculate the area consumed and power consumption.but these are not directly given in the synthesis report or PR report. whether routing resources mean the no of slices,FF etc what we get in the synthesis report? tomasulo,plz eloborate floorplanner editor. thx. Added after 5 hours 46 minutes:[/colo
In short, Advantage: save power Disadvantage: difficult to manage the timing during synthesis and STA . Besides, if something wrong, it's also hard to debug :(