Search Engine www.edaboard.com

Power And Synthesis

Add Question

115 Threads found on edaboard.com: Power And Synthesis
Hi, A lot of the time I am conducting power estimation and I have a TCF file for a specific HLB in a design and would like to extract the average data activity and average clock activity so that I can make correlation study between power estimation from synthesis tool (...)
The power consumption due to switching losses occurs maximized somewhere between steady logic levels, because neither the current nor the voltage will be null. How could the tool calculate it without any stimulus along time ?
Hi All, while doing power estimation after synthesis. i am getting not-annotated nets. How can we exactly map the names? How to solve this annotation problem? The saif file is generated using Modelsim and synthesis file from design compiler. Please help. Regards
I synthesized Leon3 with two different options: flatten-all & auto-ungroup: [/LIST It produce a single top level verlig module with all the module merged inside. During synthesis there are some uninitialized FF which cause 'x' propagation and results in incomplete annotation while doing power estimation. For that I can in
There are commands in upf to place switching fabric for power gating. Is it that this UPF can only be included during RTL synthesis and the netlist generated will have the switching fabric which cuts or supply the power whenever necessary? Is there any way to include low power things (...)
Hello, I'm designing a simple circuit using Multi Supply Voltage. I'm using synopsys Dc Compiler for synthesys, therefore I must use UPF. For the physical implementation I will use Cadence encounter which doesn't support UPF, but requires a CPF. Since my design is simple (I have only one power mode) the translation from UPF to CPF is sim
In choosing between design compiler and encounter RTL what are the points / features i should consider? In terms I want to know what points i should check while choosing synthesis tool for asic design? You could do an evaluation of each on your design, comparing QoR (timing, area, power). Cost will no doubt be im
1. report_qor (synopsys DC) - to see overall statistics of setup WNS/TNS. 2. report_timing - to see setup slack of the defined path. 3. report_power - if power is the important goal. 4. if you did physical synthesis (DC topo) - see congestion report, maybe you will need to change floorplan.
Hello, I am estimating the power consumed by my circuit post-synthesis and also post-layout using PrimeTime. I am facing a strange problem regarding the estimated power. The procedure that I follow is: 1. Get VCD file form Modelsim. I use the command ?vcd add ?r /cpu_test/cpu_inst/*? (...)
Will the power consumption for a design done in behavioral verilog and structural verilog be same?
I think report_clock_gating reports clock gating that power compiler inserts, not gating you have inserted by hand. Your gating technique is possibly a bit unreliable, anyway. I'd suggest you look in your cell library for a clock gating latch, and instantiate that.
Hi All, What are the most popular tools for power Analysis? How can they help to reduce power consumption (static+dynamic)? Thank you!
Leakage is measured in Watt. Why Dynamic power is measured in Joule ? (Watt * Time ).
power Performance Area I think now is the good time to look at the product documentation .. for syntactical help It will vary from product to product
During the RTL, the VDD/VSS ports is not necessary to be here. It will be added during the floorplan phase, when the power information is added. Also when you used a UPF/CPF flow, the power ports are only added at the floorplan phase, instead there are known from a "functional" point of view via the UPF/CPF.
Commands look OK. (Although you don't really need the ;'s and list command) You say there are lots of libraries, are you sure you selected the right one? If you open the .lib in a text editor, can you see the basic gates you would expect? i.e. FFs, nand, nor etc? Or have you selected something like a clock gating or (...)
If you can meet timing/power in prelayout, use all HVT then. Otherwise use mix mode, some time back end would be pissed off if you give them netlist not meeting timing.
Hi guys, Ive designed 5 models of squarers and wish to compare propagation delay, area and power consumption. For delay, is putting a marker at input and then at stable output and getting the difference the correct way of doing this. Also, what is maximum combinational delay which is given in the (...)
Liberty file contains a simplest timing view (simple versus spice), functionality description, power information for the std cell and any macros you need. I will say all synthesis tools must have this one to be able to transform a RTL code into netlist. and also the liberty must contains at least a flop and (...)
I am not sure if DC can be used for power estimation -- i think power compiler is the one .. not sure. Well it will read the vcd file and after synthesis it will report more accurate dynamic power - but no estimation here i feel.