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170 Threads found on edaboard.com: Power Synthesis
Dear Sir, JupiterXT have two good function of PNS(power network synthesis) and PNA(power network analysis). you can predict your chip power consumption and tool also automatic generate power trunk for you. Best Regards, chyau
Gated clock is useful not only for reducing power consumption. The digital blocks with gated clock generate much less switching noise. If your application used high resolution ADC you should care about that also.
use pwm modulation read a book for power electronics inverter the tome base trifasic is esasy if you desing a secuential machine by digital thencincs and adpater te equivalent hardware to microprocesor hardware if this is complex for you used tree ic xr 8038 (exar company) and sincronize used you uP. pic or atmel by example.
You can probably create a power spec in Encounter then take that spec back into PKS. I don't know how to do it in PKS. I assumed the flows went something like this: Classic flow synthesis->Floorplanning->P&R->P&R optimization Physially aware flow: Initial floorplanning->Macro/block placement->PK synthesis->P&R
HVT has low leakage and low speed LVT has high leakage and high speed. SVT is standard which sits somewhere between HVT and LVT. As a thumb rule, start with HVT cells and when you fail timing, you can substitute HVT cells on a critical path with that LVT cells/SVT cells. This way you will save power. I'm assuming power and timing are critical
I'm a back-end engineer. Anyone can tell me how to reduce power in back-end flow? And some tools? Thanks.
Hi, you guys with questions: To propose anything more detailed than reading hundreds of application notes and data sheets, one has to know a bit more: First: The application should be known (Voltage conversion up/ Voltage conversion down, current source, inductive heating, waveform synthesis, class D power amplifier....) Assuming that a qu
you can use vcs simulation tool to do power consumption estimation with VCD file. you can also use primepower or power compiler.
clock gating is a systemitec approach to reduce power consumption . it use latch to remove glitch.
hello.......... my friend was asked a question in an interview about how to define and where to define power and time specifications thank you..........
I want to use primepower for power estimation. I've done post synthesis simulation and generated VCD file correctly.then I used primepower commands for power estimation based on it't tutorial. but all the results of estimation are wrong because primepower consider a default 1Ghz clock not my (...)
You have to do post-synthesis simulation get vcd or saif and then annotate switching activity information back to DC by using command read_saif if you have saif or use utility vcd2saif and then annotate into DC.. For furture info read power compiler manual Regards, Dr.farnsworth
how to synthesis multi-vdd moudle for low power design! thanks Added after 11 minutes: and who can tell me what i should do in the synthesis setp for low power design? thanks
Here are some of the things to look up: 1. Clock gating inserted by synthesis tool 2. Top level clock gating (inserted by designer) 3. RAM segmentation (split up large ram into several small ones, than only power the one you are using) 4. power gating for leakage savings 5. Voltage scaling
RTL Compiler's advantages: 1) timing optimization --> from a) global synthesis, b) boundary optimization 2) area --> from boundary optimization 3) power --> from its low power synthesis infrastructure 4) capacity 5) runtime (...)
FE (First Encounter): - Prototyping tool --> floor plan, power plan,... GPS (Global physical synthesis): - Use the same keyword of "global synthesis" from RTL Compiler. NanoRoute: - Router (global route + detail route) ---------------------------------------------------------------------------- SOCE 5.2 = FE + RTL Compiler + (...)
a excellent coding style don't use any "z" in the design, except the iopad. embedded the 'Z' state shall bring some trouble suah as testable, power....
hi, i am doing ''Standby leakage power Reduction using Dual Vth in Domino Logic Circuits" project, i need some information about this.
I didnt understand whats your problem. As you said Multi-Vt synthesis is used for reducing leakage power. The timing critical paths in the design will be using Low-Vt cells for high speed. And Non Critical paths use High Vt cells. High Vt cells has less leakage power , but Propagation delay is more compared to low-Vt cells.
basic RC do synthesis is interms of GLOBALLY. Dc do optimization in the timing path. but RC first take timing (cpt) do optimization . then none critical path RC do area,power optimization. so it can achieve tradeoff between area,time ,speed