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21 Threads found on edaboard.com: Pre Sim
The capacitor's spectre view describes a special capacitor with fixed structure, dimensions, i.e. layout, and already includes its parasitics. Its layout view tells the extractor to not re-extract these parasitics. So if you use the layout view of this (same) capacitor, the pre- and post-layout simulation results will not differ by much - ju
If the cards are registering in other phones it might be because the particular carrier is restricting the equipment to what they have certified on their system. ATT in U.S. used to do this. When I worked at a major cellphone manufacturer we avoided ATT because all the engineers were alway testing pre-released new model phones that were rejected
We are in the process of putting our modem design through PTCRB, and are failing on the sim Vcc test, specifically the 3.0 volt test. Some quick notes - - We are using the simCOM sim5320A, which is pre-approved for PTCRB and AT&T networks - simCOM has been contacted but so far, has not been able to offer (...)
Hi, I am currently just getting into programming Micro controllers, and not looking to spend much money right now. While searching for GPS modules and GSM Modules I realized that most prepaid phones with sim cards have GSM modules and either AGPS or GPS. Briefly my question is, would it be difficult to locate drivers, schematics so I could try
I'm sorry. i don't know your structure so i can't give you some useful advice. Maybe your layout have some problem. you can upload the curve of the simulation about the OP both the pre and post. Did you notice any difference of the VB2 between pre-simulation and post-simulation?
the syntax is ATD+91xxxxxxxxxx; followed by terminating string.. dont forget to put semicolon at the end after the number.... ---------- Post added at 14:29 ---------- previous post was at 14:28 ---------- +(country code) ( mobile number);
I was wondering if someone could provide a comparison of what a pre extraction netlist and a post extraction netlist (with just RC extraction) in terms of the number of parasitic elements that are present in the post-netlist. Using a certain foundry, we found that the post-netlist had several hundred parasitic elements more even for (...)
Hi, I'm using Calibre PEX and Cadence Spectre to do post-layout simulation of an OPAMP. I'm using Charterd 0.35um technology. The pre-layout simulation is alright and i also passed LVS. But the Post-layout simulation is not correct, the biasing point of these transistors looks weird. Take a current mirror for example: MP10 (...)
One way to do this is to have a global clock. You configure Timer 1 to interrupt, say every 5mS. You can use Mplab sim to check the timing using a breakpoint in the interrupt routine. Use the Mplab sim stop watch to check the interrupt frequency. pre-load Timer 1 so you get a 5mS interrupt. You then use the interrupt routine to increment (...)
Most programs need some kind of clock/timer and one way to implement it is to have a global variable that is incremented in a Timer interrupt routine. You could use Timer 1 and pre-load it so that it interrupts every 1mS. In the interrupt routine, increment the global variable. Use Mplab sim to check the interrupt timing. When using unsigned
first, thanks everyone who give me help these days. now, i still have some problem. in pre-simulation, my circuit can work well. but when i extracted PEX netlist in calibre, and do layout post-simulation with the extracted netlist (with spectre), i find that, some modules' performance has some degree decrease, for ex: accuracy from 11bit (...)
hi i want to design a digital electricity measuring meter using current and voltage sensors..with features showing current units,billing amount,also last billed amount,units etc, also i want to add a feature like pre-paid scratch input units like in sim card. which micro controller fits the best for me in 8051 series.will E
I am designing an current steering dac. The dac is good when pre-simulation is done, but post-sim is bad, especially clock through effect. Please give some advice about layout technique or some reference articles, thanks.
1. netlist 2. target library 3. sdf file if U have 4. testbench which used in the pre-sim
Hi, I'm designing a two channel pipeline ADC (TSMC0.13um process, 1.3v voltage) But with my first stage transient simulation. There is a trouble I cannot handle it. You can see the transient output curve in attached picture. The green one is pre-layout sim, the yellow one is post-layout sim. Idealy the settling value (...)
In pre-sim, Bsim3 provides parameter for simulators to enable/disable the calculation of AD, etc. So you can just specify L/W for MOSFET. In post-sim, use extracted AD, etc for better match with real chips.
You may have pre and post sim mismatch.
hi, spauls Formal and STA can't replace the gate simulation(pre-simulation and post-simulation). 1). Formal tools only check the function of the design. It compare design between the different levels, and don't care the timing. 2). STA tools will check the timing of path which we don't set "flase_path" on. Now in (...)
in IC DESIGN front end means design(RTL/Schematic, sim(pre/post) back end means APR/LAYOUT
Hi AKP, You mean gate sim , Usually after synthesis pre lay out STA and Post layout STA is done.