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10 Threads found on Precharge Circuit
I wonder if the circuit has any practical use. It will take really a long to time to charge in real life, so in simulation. If finding .IC values by trial and error is too inelegant, you can spend your time in designing a behavorial precharge circuit. Not sure which approach will succeed faster.
Usually both bitlines continuously stay precharged to high; just by a read or a write operation one of them will be overwritten by a low data.
I am designing single ported SRAM with 6T cell. I am using cadence virtuoso.The components would be write circuit, precharge, sense amplifier, 6T cell, address decoders. It has to be 4 banks of 256 bits so muxes would also be required. How do I size each of them? All I know is about sizing 6T cell to minimum so it saves area.
Hi I have a problem with my spice codes. When I add the precharge circuit, the error appears. I have this problem only with finfet model. With other types, it works. .option accurate=1 method=gear delmax=30p .OPTIONS ITL1=100 .OPTIONS ITL4=100 .OPTIONS RELTOL=.01 .OPTIONS DIGSTEPBACK .OPTIONS ABSTOL=1p VNTOL=1u .OPTIONS METHOD=GEAR
For read operation, we need a precharge circuit to charge the bit lines. I know the precharge circuit for two bit lines. My question: How the precharge circuit for single bit line would look like???
ps: the gate of pmos is connect to a precharge clk in this sch,but I just connect them to gnd cause I'm using it as a combinational logial rather than a sequential one.
Dear all, The bypass capacitor of the LDO makes a very long start-up time. I want to design a LDO which can start-up within 40us, so I need a power-on circuit to precharge the bypass capacitor. Could you give me some advice in how to design a power-on circuit? Thank you very much! B. R. Ken 20070626
most on-chip buses / interconnects are of static type buses, as opposed to dynamic logic type ones that uses a precharge and evaluation periods. what i want to know is, are there any bus implemented using dynamic logic? and what is the purpose? i know dynamic logic will save space, and it can speed up a logic circuit. but does this also apply fo
hi In Domino circuit, there are two phases 1.precharge phase 2.Evaluation phase if u take a inverter, between pmos and nmos u'r domino logic will be there. MODL is basically used for iterative purposes. You can read this concepts in Industrial cmos design techniques by Uyemura
Hi I need to design a circuit to generate 1.5v~2.4v precharge voltage for large cap load(10pf). But the working environment is too tough:1.6v~6v, temperature:-50C~150C. Besides the time response should not too slow(10ns~20ns). Any suggestion or comment on it? thanks in advance! regards, joran76