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Hi Is there a switch that can make dc_compiler auto black box modules that are not available? I know that dc_exployer and primetime auto black boxes but can't seem to find the command to enable it for dc_compiler. I'm not sure if it exists. Thanks
Hello, I have just started learning primetime tool Can someone tell me about library files that are to be included with the design? Do we generate those lib files or we download it from company websites,I got mixed messages, somewhere I read that we create these files using lc_shell, and ncx etc. whereas some posts suggests downloading it from
Since there are 2 clocks and data is transferred between producer and consumer, hence we say that paths between async FIFO are CDC paths. In facts, to resolve CDC issues we add FIFO in the design. Once FIFO is in design, we generally tell STA tool (like primetime) that these paths are FIFO paths, please do not time them. Designer has taken care of
NLDM tables represent transition cell delay in the same way (the similar tables), as for propagation delay. You know, more output load -> more propagation delay -> more transition delay of the cell. You can try report_delay_calculation in primetime to see how the tool calculate real delay/transition based on the NLDM tables.
U can use the synthesis constraints itself as the base. Just source this constraints file during the primetime run...
What is the difference between Timing analysis done in Design Compiler , Prime Time and ICC Compiler. Which tool is preferred ? How do we fix setup & hold violations using Design Compiler ? Post Synthesis (library.db and gatenetlist.v are given as I/P to primetime)- How do we fix setup & hold violations using Prime Time ? Post PNR (librar
1- do you run post-route optimisation (hold,setup&drv) after routing? 2- STA tool like primetime has command to analzyse and indicate which cell to change, based on that you return on the PnR tool and fix that.
Hi, I am working on designing an SRAM that would used as part of a processor. Once the schematic and layout are done, I need to create a timing library for the SRAM module. I need the liberty for further use by tools like Design Compiler, Encounter, primetime etc. However, I am not sure of what tool can be used for creating the timing (...)
Hi: I have a question about STA. I am using Synopsys primetime . Currently, I have a design netlist, SDF and SDC constraint. There are some clocks define in SDC file. I want to know the real time that clock arrival the D-FF's clock pin. It should be clock pulse time + latency. Right ? How to use one STA command to know the real arriv
Hi everyone, I'm a beginer in VLSI design. Now I try to run primetime and export a standard to sdf file. After opened primetime-shell, I run: read_lib : import .lib file to primetime: success set link_path: success read_verilog: import gate-level netlist : success write_sdf -levels 1 -no_edge_merging {cell_delays timing_checks} (...)
primetime is only a report timing engine, you provide netlist, one timing library corner (over ...), one RC extraction (over...), and some constraint and then you report the timing/cap/trans.... You could that for various combinason of timing library/RC corner if you have this data. In general, the timing library is the typical voltage and +/-10%
Design compiler is a synthesis tool, with could report timing (and more...). primetime is at least STA tool.
Encounter timing system is equivalent to primetime, to do the STA. Encounter Power system is equivalent to primepower or now primetime PX, to do the power analysis, up to simulate and made a video where are consume the energy during one clock cycle.
primetime requires .db (compile .lib file) to work. Virtuoso could not generate .lib file, you need a characterisation tool for that.
Hello all why prime Time is called a sign off tool...i mean why people prefer prime time why don't they beleive in soc encounter timing.. I know primetime is preferred and accepted by every one as sign off tool..but what is the extra quality do prime time has that they consider it as sign off???? Please help me with this
primetime is just a "signoff" tool or recommended tool, but there are multiple tools which could report the timing. Clock Tree Report indicates, the number of buffer, worst best transition... skew reports indicates for each corner the skew.
Well modelsim simulator cannot give a power number, it could generate a VCD which will be used to a power estimation tool like primetime PX.
sdf is an input of simulator to add timing delay cell/net on gated simulations. primetime is a tool to check timing power constraints, and for the timing & power, it is recommended to used the SPEF for the R/C network and the liberty for the delay/power cells.
please post a link to the video that you are referring to Now to your questions post-synthesis STA = synopsys primetime tool post-synthesis EC = synopsys formality or cadence conformal EC post P&R STA = synopsys primetime tool post P&R timing simulation=synopsys VCS or Cadence NCVerilog simulator post P&R verification of (...)
Just want to know the opinion of the forum. Is it preferred to use exactly the same set of constraints for both synthesis using DC, and STA using primetime? Does the synthesis tool use the false path specifications, or max transition constraints? Or can we use a simpler constraint file to do synthesis, and then use a more elaborate constraint