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10 Threads found on Process Experience Cmos
First of all, how can you know "the current in the Pmos is reversed so the tool is rounding off the -ve current value to 0", have you checked the pmos leakage current in accumulation mode. Or checked the leakage current of the nmos? Which nodes are you using? According to my experience, the leakage current for older cmos process (>= 180nm) (...)
Assuming all your devices are in saturation (did you check?) , you need to increase the L of M6R M6 M4 until you get some current matching between M6R and M6. If this is not enough then you need to find another way to decrease Early effect: examples include - cascoding (very effective) - source degeneration - GD resistors (poor for matching but i
Hi, I'm woriking on some project to design a power IC with the bridge diodes to rectify the input of 40V p-p AC to DC. I'm wondering what is the considering issue to integrate in the HV cmos process. Please share with your experience if you had. Thanks in advance.
Hi, Anyone have the experience of designing the 1.8V input booster DC-DC converter with 0.5um cmos process? I have no experience of designing the 1.8V supply with 0.5um cmos process, so it is highly appreciated if you can give me some guidance. Thanks
Hi, guys: I've ever do design with TSMC 90nm and 0.18um cmos process. Design on both of these processes are well correlated between simulation and modeling. Now, I'm doing a new project on CSM .13G. Their documentation work sucks. I'm not sure how stable is their process and how good is their modeling accuracy? (...)
Hi, I am designing a LED driver with 18V HV cmos process. BUt the foundry tell me no customer used this process for the LED driver IC deisgn. Alough the process seemed to meet my design requirements. I am not sure if there is any risks because of no sucessfull mass production experience for this (...)
Hi, I need a diode varactor can integrate in IC, when add reverse bias voltage from 0~3v, the capacitance varies as large as possible. For N+/Psub diode in standard cmos process, when reverse bias voltage from 0~3v, capacitance vary only 2 times, how to get larger vary range? Anyone has experience in (...)
Hi, I am developing a cmos level output receiver with 0.5um cmos process. I have no experience for the dual supply design, what I should be careful in the design?Pls. share with me your experience. Thanks
I designed a class D power amplifier in cmos process, which is applied in audio band. Its current is up to 100mA. I heard Over-Current-Protection, Over-Voltage-Protection and Over-Temprature-Protection mechanism should be designed in such high power amplifier? Can anyone share any experience with me ?
need experience in using SOI process...