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327 Threads found on edaboard.com: Project Using Fpga
This project based on kintex 7 fpga. In simple case, I need to transmit high volume of "RAW" data to fpga. using file system isn't required. A colleague of mine had tested the free SATA II core from Opencores and was able to transfer (only RAW) data from an Artix7 fpga to an external HDD. I don't know about (...)
Hi, I am using kintex kc705 fpga board and VIVADO for following project: and it uses microblaze processor for software part. There is another project which is built over above project by adding additional compression(JPEG 2000) feature to it.
Hello, Recently I configured my fpga (MAX10) to work with CAN controller IP from open cores ( ). This core is completable with SJA1000 controller from Philips. The core is connected to Nios processor in an 8051 mode interface. As a CAN transceiver I am using SN65HV230: The initialization of the core in the be
Hi everyone! I am quite new to Verilog and fpga but I need to create a project using Verilog for Altera DE1. I have less than 2 months to finish the project. Any recommendations? Well, I was able to create simple projects like Digital Alarm Clock, 4-level Elevator System and other simple stuffs. But this (...)
Hi all, I need some help here... I am currently doing a project regarding OFDM wireless transmission using fpga. Is that possible to interface the cellular front end module (such as SST12LF02, MAX2335.. etc) with a fpga Board? Any idea?
Hi all, I need some help here... I am currently doing a project regarding OFDM wireless transmission using fpga. Is that possible to interface the cellular front end module (such as SST12LF02, MAX2335.. etc) with a fpga Board?
Hi Friends.., We are doing the mini project WATER LEVEL INDICATOR/CONTROLLER using fpga. Please, suggest me how to proceed to do project. I don't know fpga basics also. Please, give me a clear information. Thanks a lot in advance.
You can first partition your project into 3 parts. 1> Data entering the fpga(your design unit) from an external source: Do you have any info on how the data will be fed in? What communication protocol the incoming data would follow? If not you must collect info on this. 2> Your design unit in Verilog: From your description the design shouldn't be
i am new in fpga world . i need for a project a 40mhz clock, but due to bad isolation of cables the signal is really bad even at 10mhz. the clk signal has quite some ringing. Great you get stuck fixing a bad design using an fpga, bad design decisions all around. This is what gave fpgas a bad reputation at a (...)
Many fpga dev kits should work for the project. I would prefer a board with a dedicated audio codec. The Mimas V2 apparently hasn't it, just a simple PWM audio interface. Don't know about the MTE labs board. Deciding for X or A is also a matter of being familar with familiar with one or the other toolchain. Personally I'm biased to Altera. [COL
I am an M.tech student and have been working on a project related to fpga architecture this, among other things i am supposed to convert verilog files into BLIF format as a part of technology mapping.While some files are getting neatly converted,some files do not.I dont understand why. B'cuz the files which are not getting converted too
i am doing a project on the implementation of remote laboratory.Can you please help me on how to configure altera max ii ep240 to be a switching matrix using labview or quartus ii and also how do i connect the laboratory equipment onto the switching matrix.The equipment is an RC circuit:roll::cry: You write VHDL/Ver
Well you must not have used Google or maybe you used Bing (gave a lot of bad results). using google with the search string "fpga spectrum analyzer" produces a few good results and one result on the 2nd page, that would interest you. It's a senior design project for Indiana-Perdue Fort Wayne... I'm not going to bother adding a direct link (...)
Hi, please help me. I've problem on using MIG Example design. Place&route goes failed when I set Global optimization = Speed on Map properties(any other thing is not changed). I used default example design and default ISE project for MIG controller(only changed Global optimization) some info: ## fpga family: (...)
So what do you expect us to do? Do you want us to do your homework for you? You should work on this yourself so you'll learn something. When you get stuck you can post the code and a description of the problem and we can help you find/fix the problem so you can continue working on your project.
I am in need of an arcade game typically written on Verilog(.v) and not on (VHDL). I am using the Altera DE2 Cyclone IV board. Do you have any suggestions what project might be perfect for this? I am a beginner in fpga but I want to learn more. I already created a Pattern identifier, updown counter and up counter in my prev
You can't use connector J4 to communicate with the fpga. It's used only as a USB HID controller. Other then that, you can use the Ethernet port, but this will require implementing (or using an IP) Ethernet MAC on the fpga - which I think isn't a project for beginners. J13 is connected to a USB to UART IC - I think you'll (...)
Good day to everyone. We have a project about Mamdani Fuzzy Inference System in fpga. My concern is the fpga board that we are to use if DE1 is suitable with this project and how are we going to implement it in fpga. I made a lot of research about Fuzzy Inference System in fpga in IEEE (...)
I am trying to use SystemVerilog with Active-HDL tools to verify a project that includes Xilinx microblaze soft core. The project includes a software (in C) that is developed in Xilinx SDK tool. How can I include this software part (the code that is developed for microblaze in Xilinx SDK tool) in my SystemVerilog simulations?
Is it possible to find these two codes from a website and then simply combine them to get an Ethernet-to-USB adapter? Maybe. But even if you would it - you'll have to do a lot of tuning and add (a lot of) glue logic. It's never a plug & play process... This is certainly not a beginner's project. Anyways, I think you should go wit