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20 Threads found on edaboard.com: Protel Via
Im not experienced with OrCAD. However, at some CAD design tools ( protel, for instance ), whenever you update design ( SCH->PCB ), all components not related in schematic, loses net atributes. You must check configuration options. At protel, is possible to avoid that condition. +++
Hi All, Can I know what is correct procedure to import gerber file together with the via information. For first time import, my via is missing...but when i include .drr or .drl...gerber union gives me an error message...something like this "fileA.DRL is a RS274D file" "fileB.GBL is a RS274X file" "only files with the same format is allowed
Hi All, I have recently moved from protel 99SE to Altium Winter 09. I have an issue when doing a polygon pour over the top and bottom layers. It is a simple PCB and I am doing the board without a schematic - thus no net lists. I have created a manual net called GND and changed the necessary pads of components connect to NET - GND. So far so good
Dose someone know any tool which allow to prepare board like "startup generator for pcad" from CAD-HQ. i want to be able to specify the board outline, via size and track thickness to be used along with all the spacing rules. i know i can do it using spreadsheet but hoe to specify it in start up only. even older protel has this feature but orcad is
I want to know how we can tent via with soldermask on protel, PADS and Allegro? Is it possible to make it conditional vi tenting(under some component)?
Anybody knows how to create via plug layers/artwork for gerber on protel 99SE?
I have attached the Altium Designer PCB. I think you need 6.3 and up to open it. The board is contains a 56k dial up modem chipset. The left part, is the digital part, the right side, is the telephone line side device (analog part). The board is 4 layers. I have the ground plane seperated into 2 planes, one is for digital and one for analog.
Hi, everyone. I have some questions about drawing buried vias connecting two conducting plates on a 4-layer PCB by using protel DXP. My questions are: 1. How can I define the buried via connecting ground plane and intermediate copper layer with square conducting patches on it? Actually it seems that I cannot directly place the (...)
Hi, everyone. I have some questions about drawing the mushroom-like EBG structure on a 4-layer PCB by using protel DXP. My questions are: 1. How can I define the buried via connecting ground plane and intermediate copper layer with square conducting patches on it? Actually it seems that I cannot directly place the via/hole on the PCB (...)
Hi, everyone. I have some questions about drawing the mushroom-like EBG structure on a 4-layer PCB by using protel DXP. My questions are: 1. How can I define the buried via connecting ground plane and intermediate copper layer with square conducting patches on it? Actually it seems that I cannot directly place the via/hole on the PCB (...)
Hello Everyone, Can anyone briefly explain to me what is that? by looking at the sample above, it seem like a data report about holes,trace,component(sizes,count,etc) My question is.. am I able to generate such report via protel DXP?? Thanks in advance...^^ Zen
Do u know how to generate odb++ export files in protel DXP
I have one simple question about protel DXP: How to specify the plane cleareance? In design-rules-plane-power plane clearance, there seems to be possible, but when I want to change the clearance value where the first object matches Net and Layer, it seems no change in the PCB. I need to change the value of Antipad between the via connected to th
depends on what software ur using, most u could specify which layers u wana route. example, in protel u could set this in the design rules. in orcad layout u go to layers manager. happy routing then..
Hi all, I'm new to RF design and need your help. Here are schematic and layout of my 910 MHz feedback oscillator. The layout is unfinished, because I have not mastered the ADS layout function, which is quite different with protel. Some questions: 1. How to use the bottom layer (cond2?) as ground plan? 2. How to put a via to connect a pin to
you can set the net rules , the layer for routing etc. also the via u can asign for nets. iam not sure in protel. but in most eda tools this concept is true. binu g
protel doesn't do central cutouts yet. The only way to get the representation you want is by using a pad for the hole. A polygon to the edge is done by using a keepout boundary, then copper flooding. The flood will stop at the keepout (you can make the keepout boundary as narrow as you need to make the proper shape and limit).
Hello : I am running protel DXP DRC. I got lots of warnings. one of them is like: Net SD1 Warning - Pad/via touching plane Does anybody know what is exactly meaning? How can i correct? Thanks.
The warning is trying to tell you to check all your vias and pads that touch the boundary of the plane split. protel has no way of checking if the overlap of pads, vias and internal plane primitives has partially or completely broken a connection. The warning serves as a reminder to check each pad and via where such an (...)
clearance constraint for what? parts? tracks? which protel version? :R