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519 Threads found on edaboard.com: Pspice Model
Hi This is my first post here :) I try to use HCPL-316J model which is download from Avagotech site, but i think this model work bad in pspice. Whatever i connect on input, try to work with inverting and no-inverting input, i got same output, no change in output signal :( I think that output signal need to follow input signal, (...)
I have a design which used a part (a spice behavior model) only for pspice simulation purpose. How do I produce a netlist for PCB Editor without removing this part from the schematic page? Put it another way, is there a way to tell Allegro to not use this part when generating a netlist? Thanks.
** Creating circuit file "V1_5025_trial.cir" ** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS *Libraries: * Profile Libraries : * Local Libraries : .LIB "C:/lm5025-Library/lm5025.lib" * From section of C:\Cadence\SPB_16.5\tools\pspice\pspice.ini file: .lib "nom.lib" *Analysi
Use the ZX subcircuit from the MISC.LIB (s. the MicroSIM pspice Application Notes, pp. 159-160).
The OLB is the library, the LIB is the SPICE model(you should be able to view that with a text editor like Notepad). The IND is an index files I think. If you show a link to the files you have downloaded I can have a look unless a more experienced Orcad/pspice user can chip in first. Keith
hi i am a student and it my first time that im working with pspice.I have work to do....I need to create a dc/dc pspice model (part) With the following properties: Vin:20-48V Vout(min):19V Iout(min):10A I tried to look online help ... or models from different manufacturers, but for everyone if the output current (...)
Hi, I am currently building Push-Pull converter 12V to 315V 600W 50kHz. I am trying to use UC3846 controller as it seems like properly designed circuit is very robust. I hope someone can help me finding pspice model of the UC3846(or UCx846 or UCx856) chip, or even better if someone has similar simulation completed. Thank you very much in advance
pspice has a 4046 model in mix_misc.lib, as the library name suggests, it relies on the mixed signal simulation option. Other models have been mentioned in previous Edaboard threads.
As a rule, foundries don't use or support pspice as an IC design tool. They produce pspice netlists for the convenience of their customers in developing applications, but these seldom embed the transistor details - these are part of the "secret sauce". You might be provided model files that are HSPICE or Spectre compatible, from which you (...)
Hi all, I am using pspice 9.2 and trying to have the memristor model given in simulation the programs gives: "INTERNAL ERROR -- Overflow in device x1.G1, Convert". the model memristor is: My code is: *******************************************************************************************
So I am trying to model a AD620 inamp from anolog devices and have their Lib with the AD620 in it and am trying to use that with a basic circuit. I am new to Capture CIS pspice and cannot seem to get the circuit to work without the convergence failing. I thought it might be a floating ref point, but everything is grounded so I am not sure where I a
I have been trying to make a variable capacitor based off of a lookup table in pspice. I found a paper by cadence, A Nonlinear Capacitor model for Use in pspice, which gives a method of creating a variable capacitor but I am unsure how to actually write the .lib file to implement this design. Any assistance would be appreciated.
Hello, Currently I'm working on the LDO reg. pspice macromodel but I have some concerns about the output noise modelling. After studying some papers on Op-Amp macromodels I was able to obtain fairly good match between the Output Voltage Noise Density Measurements and Simulations in 10Hz-1MHz bandwidth. (The noise source (...)
Use the parts from libraries present under ../tools/capture/library/pspice folder.
That's disturbing though, I wonder how many other broken models came with pspice? Unfortunately I don't know. You should be watchful and always check the plausibility of simulation results. The present case is a very obvious case of a "broken" model. More generally, pspice models don't represent all (...)
Dear mohadese Hi As i understood you want simulate internal circuit of a 741 op amp in pspice . when you are talking about what transistor should be sued , it is important to know , specification of transistors are pretty important . e.g maximum and minimum beta of transistors , maximum value of IC of them ( as you probably know in each opamp t
Respected members I need some urgent help and thanks in advance if someone could provide 1- pspice model or implementation statement for Ideal (zero delay) SPDT/Analog MUX 2- An ideal model(zero delay) of Transmission gate?? Any little help would be highly appereciated!!
Hi, I've been working on a power device macromodel based on abm, but I got stuck in convergence issues (transient analysis) when Vdd goes over 100V I changed RELTOL, ABSTOL, VNTOL, etc., but I wasn't yet able to have it working with higher voltages. The model is in the attached pdf. I am using pspice from Cadence SPB v16.3 Any (...)
I cant find the tsmc cmos 90nm spice model on the internet to use it on pspice ... does anyone have it pls ?? I used to work with the tsmc 90nm model on virtuoso but i dont have virtuoso anymore as i am not running on linux anymore and now i have work to do for my university using the tsmc 90nm cmos and as i am currently using (...)
Hi all, I am trying to simulate a JFET in orcad pspice and i am facing the following problem The pspice calculation of the drain current is different from my hand calculation. Could somebody please explain me where am i making mistake? The JFET iam using is J2N3819 and the model parameters are .model J2N3819 (...)