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Ram And Fifo

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27 Threads found on edaboard.com: Ram And Fifo
Here is a picture of the Dual Clock fifo used to "transmit multi-bit signals from one clock domain to another" and it is "usually implemented as a wrapper around a dual port ram". It is from a book. 131786 It is not clear to me when exactly are the signals full and empty asserted. Why does signal full only goto the "wr
if you need registered output, you register the output. if you don't, you don't. it doesn't matter if the fifo is built with flops or sram.
1.Convergence-> Feed a synchronizer only from a flip flop and not from combi logic. Divergence -> Synchronize a signal only once from 1 clock domain to another. Don't generate multiple copies. 2. What is a dual port ram synchronizer? Never heard of it before... 3. A fifo internally has a ram along with other (...)
it's a small, fast, open source, command-line verilog simulator. i have successed to use it in a X* fpga design, which is a middle size and include ram/ fifo/ mac-ip etc. the result is equal to commercial tool. it supports lxt/lxt2 format, so you can dump wave and show them by gtkwavw tool. (...)
FPGA fifo IP is based on block ram and in so far using the same storage. You'll use a fifo if you exactly need fifo functionality, otherwise design the function you need with block ram directly.
Dual port Bram is the perfect way to cross a clock domain. Even better use a dual clock fifo so you know when data is available (it will contain block rams). You will need to use coregen for the fifo, but block rams can be inferrred.
Guys, I have a variable like this : unsigned char idata pat7 = {0xFF,0xFF,0x18,0x18,0x18,0x18,0x18,0x18,};//T unsigned char idata pat8 = {0xC0,0x00,0xC0,0xC0,0xC0,0xC1,0xFE,0x3C,};//j unsigned char idata pat9 = {0x18,0x18,0x00,0x18,0x18,0x18,0x18,0x18,};//i unsigned char idata pat10 = {0x83,0x43,0x23,0x13,0x0F,0x13,0x23,0xC3,};
Please look at this example code designing a synchronous read/write fifo by instantiating a dual port ram: Synchronous fifo
hitech, You could take the bit stream, convert it to words, 8-32 bits. You can then store those in a fifo and take them out on the output side of the fifo as needed. A fifo can be implemented in a duel port block ram. One side is writing the bits, converted to words, and the other side (...)
if CLR = '1' then for i in 255 downto 0 loop fifo(i) <= (others => '0'); end loop; elsif ... is it possible to actually implement something like this? A fifo is a memory and accessing all the 255 elements in one clock cycle is impossible if the fifo is inferred as ram in FPGA. If the (...)
Hi all!!! i would like to know how to design a fifo and fifo depth calculation. Pls post useful links on fifo i have read of self timed fifo and dual port ram implementation.. but i am cannot fully understand the read pointer and (...)
reg ram ; How big this ram actually is? is it 14bits by 3 slots or 14x8 slots ? by incrementing counter we get cell adresses from 0 to 7 and by shifting 1 we get 3 x 14 bit memory ocupation. What is right? I thought that it is 14x3 but after studying the fifo verilog code:
hi i'm new at vhdl programming, and I want to learn it as possible as I can. I have to make a fifo ram, with 2 clks, but I don't know any special thing about 2 clks in one ram,and of curse I have to make a ram with read and write ports, (...)
Dinesh, It depends on application whether u go for fifo or Block ram. If U want to process data before sending to outside again and that processing depends on old data too( in case of filtering) then option is go for ram, here fifo will not work. So depending on your application, u need to (...)
I encounter the following error during compilation in precision synthesis: "Instance instance... fifo.... has no lut_function or eqn property" Does anyone knows what's wrong? This warning applies to all my XILINX core gen fifos and ram.
If you are using xilinx devices it's too easy. Xilinx devices have block ram which are dual port/ you can easily use it as a dual port fifo with different width. It's too easy check xilinx documents.
My short answer is: Try it and see -- that's how to learn ISE! (Sorry about the bad rhyme.) Longer answer ... If you select 8 bit width, coregen will configure each block ram as 2Kx9, and then it will use 8 of those 9 bits. Your FPGA provides 20 such block rams. I don't know which fifo Generator (...)
fifo - first in first out --- u can use ram for the fifo but it shud follow the fifo concept. Next read address shud be prev read pointer + 1 only n same with Write pointer. Most of the designs, they won't use ram, due to its 2 clks delay while writing it and also the error probability... (...)
I had a quastion in my last interview: Implement a fifo while you have Sram only (thereis no DPR). the CLK system is 50MHz. or how you may implement DPR by Sram??? @50MHz ------------------------------------------------------- Actually I don't understand how make Sram read and (...)
Sounds like a good project! Instead of using a regular ram, consider a fifo. It can write and read simultaneously, and it already contains the address counters. One popular fifo manufacturer is Cypress.