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115 Threads found on Random Sequence
is it possible to get the reverse sequence generated by a LFSR? I need a pseudo random sequence, and the same sequence in reverse order I read that the output stream of a LFSR can be reversed by mirroring the taps. This did not work, however :/ - - - Updated - - - It's not possible
1)How to select initial random matrix for 3 input circuit(ex.Full adder) An FPGA can initialize a block RAM (the matrix storage) from configuration if you provide the initial values to the core generation tool. Otherwise you will have to initialize the RAM by writing a prbs sequence to the RAM as part of an initialization
Hi all, I am trying to use true random values to feed my testbench for functional simulation. I am using the random package from OSVVM but the sequence is pseudo random. Is it possible to use system time to generate the seed in VHDL? I want to use the system time not simulation time, so i have different values each (...)
I have a parallel bus of 32 bits changing value on every clock cycle @ 50 mhz I need to detect pattern 0111111111111111111111111111111 (bit 31 is a zero) The pattern can start at any bit position of the parallel bus This mean that I can get the 'zero bit" on i.e bit 19 of the parallel bus and I will have to look at the previous w
Hi, I am reading Behzad Razavi's "Design of Integrated Circuits for Optical Communication". In Eq. (2.2), it describes the power spectrum of a random binary bit sequence as, Sx(f) = (1/Tb) * |P(f)|^2, where x(t) = Σ bk * p(t-k*Tb) for bk = ?1 and P(f) = Tb*sinc(f*Tb) Since x(t) toggles between +1 and -1 with equ
Hello, I have a 2-port SRAM, the operation is that the read and write operation are simultaneous. But read operation is in sequence, like from 000 to fff, but write operation is random. The problem is that they may read and write a single address at the same time. Will this result in wrong operation? For example the read data is crap, neith
Hello, I design an inductorless Chua circuit based on the design found in and by replacing the LMC6482AIN opamp by TL081 The circuit works but when I tried to connect the output with comparator (open loop TL0821 opamp or LM311) the output signal was vanished. I tried to couple the two
Hi, I'd like an explanation of the PSD of a sequence of independent random PAM symbols or amplitude +1 or -1. Now any standard textbook tells us that the PSD is the Fourier Transform of the autocorrelation of the signal, in my case the symbols are INDEPENDENT and => the autocorrelation is non-zero only over the symbol duration 'T', beyond this
thanks, but that generates periodic pulse, right? i want to generate random binary sequence
Hello, In an AGC system the 3-db bandwidth is 7.5 GHz with a ((2^15)-1) pseudo-random bit sequence at 5-Gb/s. any one can tell me what is the relation between data rate and 3-db bandwidth and what is ((2^15)-1) pseudo-random bit sequence? and for example if the 3-db bandwidth is 9 GHz what would be the data rate? with (...)
Dear all, How to assign a voltage source whose duty cycle is random in HSPICE? Many Thanks always for ur helps.
I have 2 sequences in UVM which need to run on same sequencer in parallel. e.g. seq1 generates 10 pkt viz pkt1-pkt10 with some random delays in between. seq2 also generates 10 packets of same type pkt11-pkt20. I fork these both seq1 and seq2 and what i see that packets are either generated in 1-20 or 11-20 and then 1-10 so it means (...)
i modified the example random number generation program from keil help section. keil example program #include #include /* for printf */ void tst_rand (void) { int i; int r; for (i = 0; i < 10; i++) { printf ("I = %d, RAND = %d\n", i, rand ()); } } my program was #inclu
I am using a Bernoulii Binary Generator to generate my data signal for a Direct sequence spread spectrum model I am designing on SIMULINK. The specifications of the generator block is as follows : Probability of zero : 0.5 Initial seed : 61 ( random number ) sample time : 0.6 Frame based outputs Samples per frame : 100 I wish to calculate
Dear All I'm Looking for float random number generator in VHDL code. Any suggested Code ? Megahady,
For a car-fob, when a certain code have been accepted by receiver is it automatically blocked against reuse. Else had it not been a working rolling code system. A common rolling code system is KeeLoq which have a 32 bit random sequence generator. When a key fob is paired in a such system, do it get a synchronized window, 256 steps wide, in case
Hi, I am testing my TX which is a MUX based TX for pi/4 DQPSK modulation. I am using an AWG to generate the random binary sequence for the state machine controlling the MUX. First I tried the sequence so that all phases (0,45,90,...315) get transmitted. But due to periodicity the output spectrum has narrow lobes. Then I tried a 2000 (...)
@Trickedeasy Whether the seed are initialised to a particular number or left uninitialised, for both cases, same sequence of random number are generated I think this is not true for a LFSR generator. probably you could not load your LFSR correctly or mot simulating enough time. I need random seed values after each cycle of
In my systemverilog testbench, I need to genrate a 32 bits sequence which randomly contains 5 to 27 bit "1". Can anyone help me to describe the constrant of this random bit-sequence? thanks a lot
it's true. from keil documentation The rand function generates a pseudo-random number between 0 and 32767 it's mean every time you restart your program it's generate the same sequence of numbers. You can use srand() function for each value it generate different sequence. Show this link