Search Engine www.edaboard.com

Realtime Verilog

Add Question

7 Threads found on edaboard.com: Realtime Verilog
Hello everyone, Im trying to write a verilog-A Vpulse whose frequency is supposed to be 50M at 0-15us, 51M during 15-20us and 49M during 20-25us. How can I do that? What kind of operators or expressions are suoopsed to be involved in the coding? Timer or $abstime or $realtime? Thanks a lot for any answer!
ime is a 64-bit integer type value, which will always ignore fracional part. Whereas, realtime can store a real value for simulation time. As you may be knowing, verilog has inbuilt system tasks $time and $realtime. $realtime gives the real value of time. However, the precision depends on the timescale precision value. (...)
i'm currently doing a simulation debug involving calculations. The real numbers i'm interested to observe involve some maths regarding $realtime. I believe something's wrong in the behavioral model of the PLL when it's calculating the period of the refclk/fbclk etc... Unfortunately, the data stored as "real" cannot be pulled out as sim waveforms
Hi all, Im looking for some books about implementation some DSP algorithms into FPGA (mainly realtime image/video processing). So far ive found that these ones might be interesting: - Design Recipes for FPGA Amazon.com:
Hello, It's about a ModelSim error massage: "near "EOF": expceting: EVENT INTEGER REAL realtime REG TIME AUTOMATIC IDENT STRING" Does anyone know what the message mean? Thanks very much It is a syntax error in your verilog/SV source code. Show us your code if you need more help. Ajeetha, CVC
`timescale 1ns/10ps module foo(clk); input clk; real t0; real t1; real frequency; initial begin @ (posedge clk) t0 = $realtime; @ (posedge clk) t1 = $realtime; frequency = 1.0e9 / (t1 - t0); $display("Frequency = %g", frequency);
That code looks like an oscillator. The derivative of sine is cosine, and by adding a small amount of one to the other, you get oscillation. If you need precise amplitude and frequency, that's not a good way to do it. For testbench simulation, try simply using verilog's $sin() function, maybe combined with $realtime.