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AC motor driving logic with panel

An industry standard VFD allows to adjust the motor voltage independent of the frequency, in so far you can reduce the motor power. Because friction losses of an induction motor are pretty low, it's possible to run the motor at reduced power. But that's only possible if the load torque is respectively low. Is it so?

Flyback Transformer Design (48V in, 12v out, how to layer turns, leakage inductance)

1. 1 layer pri, then 1 layer sec, then 1 layer pri, then the final sec. or Leakage inductance will be reduce ? th of regular primary secondary winding but inter winding capacitance will be double. Wave form rigging will be very less 2. 2 secondary layers directly together sandwiched between the two single primary layers. Leakage inductance will

Washing machine pump speed control, voltage drop down.

A variac is just the thing to slow pump speed, assuming it really would reduce noise. * Just as an experiment I would try putting a resistive load in series with the pump. Say, a space heater. Maybe a high W bulb (or a few low W in parallel). Enough resistance to drop the pump to 70 or 80 percent of normal power. See if noise level drops. * Noise

Reordering algorithm

Hi, This is the reorderng algorithm use to order test patterns to reduce switching activity.can anyone help me to understand this algorithm. step 3 & 4 are confusing..... Reordering Algorithm The various parameters used in the algorithms are as follows: t, t, ? t be n test vectors with m bits each. 12n T={1,2,? k ? n} where k represent

AR-Filter settings in CST Microwave Studio

Hi, I've got a very large and resonant structure and I'd like to reduce simulation time by using AR-Filter option in CST. This option needs to setup some parameters. Is there someone who can help me to setup this function please? Thank you very much for your support!

Reduce the ringing in Vivaldi antenna at center frequency 2GHZ

Hi all, could you please help me to find some ideas to reduce the ringing in Vivaldi antenna at center frequency 2 GHZ? Best regards

Leakage issue in forward converter

The leakage inductance example results in < 10 mW snubber losses and shouldn't involve design problems for a RCD circuit. The low Vds rating imposes a low switch duty cycle and tight snubber dimensioning and doesn't sound reasonable. Although C555 can drive MOSFET gate you'll probably want a dedicated driver to reduce switching losses. [COLOR="

NO vs NC Relay to reduce seizing

Currently have a relay thats rated for 15 amps for a 5amp AC PSU power source (high capacitive inrush current). I have it wired so that its in the NC state, and when the relay is powered it cuts power to the PSU (reason I want it like this is if the relay control logic fails on boot/power on, the AC circuit will still be closed and providing power)

Hello friends, I try to figure out the best option to have adjustable load current for this charger 134680 I have a external device that may experience low temperatures for several days (-10 deg C or more). The battery is a special Li that can be charger from -10 normally and up to -30 deg with reduce rate of about 0.

Connectong two or more varicaps in series to reduce minimum capacitance?

If a differential mode is not considered, I'd prefer to use single varicap but lower cap. values.Because series connected varicaps wil have higher loss parasitics such as package bonding inductance, series resistances etc. so each parasitic will reduce the overall quality factor of the tank circuit.

Is it some kind of start delay or transient filter circuit?

Out of context I can't be sure but it looks like a circuit to delay the rise of the regulator output as the 3.3V line rises. C54 charging through R22 will cause a slight increase in voltage at the ADJ pin which in turn will trick it into thinking it has to reduce it's output voltage to maintain regulation. D1 will be to discharge C54 again when t

Design for a Pure Sinewave Inverter, what is easiest and cheapest to implement?

The step-up transformer is ideal if we want ease and simple construction. Use an H-bridge to apply true AC 50Hz square waves. Shape them into a sine by installing a series capacitor. Thus you reduce problematic spikes which tend to happen when switching inductors. This is a basic schematic showing

Buffer stage: CD vs CS

A common source stage will only be a unity gain amp either under very specific bias, load and process conditions, or when driven in a feedback loop. It will be hard to stabilize across all. The common {source, emitter} stage is a voltage amplifier and to reduce its gain to 1, needs a (compensating) fractional gain. And because gain variabi

Wilkinson power divider design.

How to reduced the size of Wilkinson power divider?

Step down a LiPo battery voltage

6 LiPo cells in series will drop to about 3V each when discharging (18V) when they should be disconnected from the load. If you reduce the voltage 1V then the total voltage will drop to 17V. The wires on a Lipo battery are thick because a LiPo battery can produce many amps of current. Thin wires on a diode melt with a high current. A 1N4007 can blo

Interfacing with a 3.3V uC on a 14V PWM signal

No sense to use optocouple if you are using same ground. No sense to use zener diode and e.t.c. Emitter goes to digital ground, collector directly to pin with pull-up resistor. Zener protection actual only on left side. Not even zener, TVS! And ceramic capacitor to reduce ESD.

LM386 low noise alternative?

If you built the Correct Circuit, using Pins 1 & 8 for gain, it would probably be better. And Anytime your Powering HEADPHONES from ANY POWER AMP, You should Include a 100 Ohm Series Resistor going to the Headphones. Both these Will reduce that Noise. The Resistor will protect the headphones from getting too much Power and protect your Ears from

Measuring leakage current in 3-phase system with current transformer

Referring to you original question, a possible configuration to reduce errors by non-ideal core is a compensating feedback circuit that zeros the total flux.

pic micro with 90% rom

Considering that the compiler that you are using could be already configured to optimize program memory usage ( usually to detriment of speed ), even on this case it is always possible to reduce the code size by better structuring the program, and it is achievable only depending on the inventiveness of the programmer to have creative insights, and

how to reduce conjestion in a perticular clb

what can I do with this information to reduce congestion in the design ? If your design meets timing constrains - why would you bother with congestion reduction of a specific CLB ?