1000 Threads found on edaboard.com: Reduce
Subharmonic oscillation cannot happen at small signal. It is a large signal phenomenon which appears in peak current mode, mainly when the duty-cycle is greater than 50%.
Definitely this is not our case.
Just reduce the number of turns of the inductor and you will get the right fundamental frequency.
RF, Microwave, Antennas and Optics :: 10-07-2016 06:23 :: vfone :: Replies: 22 :: Views: 1845
Without going into the design details (AES encryption details)...
What can be done is already mentioned in simple English #1 to #3.
If you cannot use a larger device (#1) then go to #3.
I am assuming you have specified the correct no. of top-level ports (#2), else re-check.
If #1 is not feasible then #3 is your only option. reduce the encr
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-06-2016 09:02 :: dpaul :: Replies: 8 :: Views: 1152
i found a graphical LCD driver chip, NT7538 i.e. ( other LCD controllers have same mode too)
in the datasheet, about "standby mode" is written:
Stops the operation of the duty LCD displays system and turns on only the static drive system to reduce current consumption to the minimum level required for st
Professional Hardware and Electronics Design :: 10-06-2016 08:53 :: hm_fa_da :: Replies: 2 :: Views: 563
Your attachment does not work so we do not know the function of the circuit.
The AD8610A low noise opamp has a typical open loop gain of 250 at 100kHz. Is it needed to reduce 100kHz distortion? It costs 2.8 times more than an OPA134 audio opamp that also has low noise and has an open loop gain of 100 at 100kHz where its distortion will be about 0.
Analog Circuit Design :: 10-04-2016 21:38 :: Audioguru :: Replies: 9 :: Views: 810
What about you reduce delay times by a factor of 1:50 for example? The above routine is doing absolutely nothing for 1.4 seconds (even w/o accounting debounce time), and writing in 6 memory locations in perhaps no more than a hundred millisecond. The whole funcion at all is masking the read of the Button() exectution for a long period.
Microcontrollers :: 09-28-2016 17:13 :: andre_teprom :: Replies: 13 :: Views: 869
i want to simulate 2 layer pcb and calculate s parameters. this 2 layer pcb have complex structure . in cst micro wave studio with frequency domain solver its have too long time for simulating and not appropriate . can any one help me to reduce thats needed time for simulation ?
RF, Microwave, Antennas and Optics :: 09-28-2016 12:06 :: amir_rch :: Replies: 0 :: Views: 574
If I am having set up violations in this situation, how can I fix it?
As a front-end logic design engineer I insert re-timing flops on the path, if the design allowa it (try to do an operation in two clock cycles instead of one). The newly inserted flop will reduce the long path.
ASIC Design Methodologies and Tools (Digital) :: 09-20-2016 07:31 :: dpaul :: Replies: 10 :: Views: 991
What are the ways to reduce these run times ( I cannot modify the rtl codes, I know there are combinatorial loops )
Already answered in #1
Also How can I efficiently utilize the time while its getting implementing. Anything which I can do in parallel to get results of multiple optimization techniques symultaniously or at leas
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-15-2016 07:55 :: dpaul :: Replies: 11 :: Views: 495
The aim is to prevent the battery going over 14.4V, and to prevent 'gassing' (bubbling electrolyte). Battery voltage is elevated during a charge. Afterward it takes several hours to settle down to its resting voltage, 12.8 V.
A taper charge is optimum. Start to reduce charge rate when battery reads 13.5V. reduce steadily until final voltage is 14.
Microcontrollers :: 09-12-2016 15:40 :: BradtheRad :: Replies: 2 :: Views: 752
First stage output/second stage input node is high impedance, too.
Diode connected? I don't see a diode connected MOSFET. The compensation network will of course reduce the OTA output impedance, as well as the input impedance of the second stage.
Analog Circuit Design :: 09-11-2016 17:57 :: FvM :: Replies: 2 :: Views: 547
I will suggest to work in the following way to reduce the simulation time
1. Define relatively thin mesh as mesh directly affects both the simulation time and accuracy so you can make a good bargain.
2. Try to reduce the maximum number of passes that will reduce the simulation time but again at the expense of accuracy but most of time (...)
Electromagnetic Design and Simulation :: 09-07-2016 14:41 :: nomigoraya :: Replies: 6 :: Views: 1017
You did not mention so far for what kind of application all the 6 motors will be used, but if there is the need of real time geometric calculations to be done by the uC ( eg not synchronized steps, but interspersed at non-integer rates ), the use of delays will ruin the operation - or at the best case, will dramatically reduce the maximum speed of
Microcontrollers :: 09-06-2016 16:35 :: andre_teprom :: Replies: 11 :: Views: 724
In normal operation, there's no need for a series resistor. To calculate a resistor that protects the opto triac under all conditions, including load short, apply ohms law. R = 250V/0.07A = 3600 ohm.
Unfortunately, the series resistor would reduce the load voltage in normal operation to 70% (assuming a resistive load) and must be rated w
Power Electronics :: 09-06-2016 07:29 :: FvM :: Replies: 6 :: Views: 541
MNA-MAT, a MATLAB based analog circuit simulation tool, uses Modified Nodal Analysis to reduce a SPICE netlist to a system of equations which yield voltage at and current through specific points in the network. Monte Carlo analysis adds further functionality by evaluating possible uncertainties in real-world working conditions.
Business, Promotions, Advertising :: 09-02-2016 14:15 :: nik1106 :: Replies: 0 :: Views: 1068
Hi. I want to regulate a 45VDC unregulated power supply down to 300mA at ~12V. I was going to use a LM7812 until another member pointed out they have a max Vin of 35V. My plan was to use the circuit shown on the
Elementary Electronic Questions :: 09-01-2016 07:02 :: JohnJohn20 :: Replies: 7 :: Views: 727
Due to skin effect of 0.6 um, most of the current flows on the edge, so will it be a good idea to assume sheet metal to reduce simulation time drastically? I've simulated several single-patch antennas and I didn't see a big change but if I try to simulate full-sized antenna with thick metal, ADS creates over 100,000 elements and my computer literal
Electromagnetic Design and Simulation :: 09-01-2016 18:43 :: usx :: Replies: 1 :: Views: 436
Two or more frames to animate means that your simulation time is very small or the probe setting you are using has very big step. This may be the reason you can check this by increasing the simulation time or if you are using any probe then reduce the time step.
I never got this error with HFSS but I am optimistic that by making one or both mention
Electromagnetic Design and Simulation :: 08-31-2016 07:14 :: nomigoraya :: Replies: 11 :: Views: 922
How can i reduce step size for faster simulation?Analysis time step is determined by "reltol", "relref", etc. parameters in Cadence Spectre.
I already tried option in transient analysis for TIME STEP PARAMETERS but it is not working.You can not control analysis time step even if you set
ASIC Design Methodologies and Tools (Digital) :: 08-27-2016 09:57 :: pancho_hideboo :: Replies: 3 :: Views: 738
In my design, I am having some congestion after post route stage. What are the different methods I can use to reduce the congestion without going back to the previous stages?
ASIC Design Methodologies and Tools (Digital) :: 08-17-2016 10:41 :: biju4u90 :: Replies: 2 :: Views: 475
Hi. I have a 12V PSU which I want to reduce to 4V 2A PSU. I have used a NPN power transistor (BD137) plus a 270Ω resistor and a 5V zener to make a regulator which gives me a 4.4V output which is still too high.
Is it a good idea for me to just put a silicon rectifier of some sort in series with the regulator output to give me a further 0.6V
Power Electronics :: 08-15-2016 06:56 :: JohnJohn20 :: Replies: 7 :: Views: 412