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19 Threads found on Register Clock Pins Clock
Hi, Normally, you wouldn't add so much of logic to the reset condition in RTL and you wouldn't use the sequential clocking block always @ (posedge or negedge) for signals other than clocks and resets. If you want to sample the address pins , assign the incoming address to a register on (...)
The output on pin 7 is your best debugging tool. Enable the DS1307 registers to output a 1 Hz signal, and connect an LED (with a series resistor) on its output. A properly working unit will display a blinking LED.
Just make sure you have these settings: In the OSCCON register the IRCF bits should be set to 01. In CONFIG1 register, PPLEN (bit 12) should be 1 and FOSC (bits 2, 1, 0) should be set to either 100 or 101. Use 100 if you want RA6 and RA7 to be normal I/O pins. Use 101 if you want RA6 to be a clock output (...)
Does the datasheet mention that there is internal pull-up for I2C pins on PORTC? If yes, is the pull-up register is WPUC? If yes, then configure it.
The symptoms suggest there is more than one clock pulse and the 'B' input is propagating throughout the whole shft register. The logic levels shouldn't be a problem but noise on signal edges might be, particularly the one shot signal. Just temporarily, try connecting a capacitor (say 100pF) between pins 7 and 8 to see if it (...)
Did you check whether your SPI communication happens properly. Most of the time due to different problems in register settings, SPI communication does not happen. Check the SPI communication pins with an oscilloscope. If you can see clock lines and data lines work, then read the datasheet throughly for proper timings & (...)
Skew is the difference between the arrival times of clock to the clock pins of register insertion delay:- The delay from clock definition point to clock pin of register if skew is maximum then timing will (...)
hai in p and r flow , i am seeing many registers's clock pin with no clock ( in the reports from synthesis) . Some of these clock pins are connected to clock gaters ( their input is coming from (...)
Without sufficient pins left to connect 8 buttons, you obviously need some kind of expansion logic. There are many options, don't know which is easiest to you: - a serial shift register to read the buttons. Advantage: can be easily expanded to more inputs. Uses shift clock, serial data in and load output. e.g. 74HC165 or (...)
how to interfacing PIC16F877A with shift register 74HC595 and led? i need the help on c++ source code using MPLAB~ do i need to write both source code separately: 1) source code for interfacing PIC16F877A with shift register 74HC595 2) source code for interfacing PIC16F877A with led
Hello All, I need to have 2 multiplexed clocks in my design (2 pins multiplexed internally from control register). Signal from multiplexer output I want to use as system clock. So, what is the right way to do this in terms of Encounter RTL Compiler synthesis scripts? What parameters I (...)
I came across many definitions for clock latency... Def 1: The number of clock pulses required by the circuit to give out the first output. Def 2: The total time taken by the clock signal from the source to reach the input(clock (...)
I wonder tthat how the clock latency influences the timing. In my opinion, if clock latency is worse. Then all the arrival time of the clock will be delayed equally to the register clock pins. So which aspect will be (...)
Hi, Has anyone interfaced a 74HC595 with AT89S52 or similar microcontroller? If yes, any pointers would be helpful. regards, Seemanta
Use shift register that you can drive with simple synchronous serial interface. You can use any two pins to generate clock and data to shift register.
TetraMax report a S1 violation . ERROR : chain 3 blocked at DFF gate after tracing 0 cells. register clock show 0X0, so trace clock to a DFF. clock from DFF. DFF show 3 pins : RN :111,D:111,CK:101,BUT Q: XX1,just Q connect with (...)
JTAG boundary scan started as a method of testing ICs and their interconnections using a shift register built into the chip so that inputs could be shifted in and the resulting outputs could be shifted out using only four I/O pins (clock, input data, output data, and state machine mode control). This eliminat
Dear all: In my design, it has some derived clocks and uses a MUX to select one as the registers clock. But when I synthesize it in RTL compiler. I got these messages The following sequential clock pins have multiple (...)
hi all, I'm trying to output data from a design I implemented on the Altera APEX FPGA. When I analyze the data that is outputted from the pin, there seems to be distortion and the data that is outputted is wrong. The data connected to the output pads of the pins are directly from a register. So it can be assumed stable between (...)