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27 Threads found on edaboard.com: Register File Memory
Is it possible to custom design a memory cell for e.g. multi ported register file or multi-ported reservation station and have place and route tools build a memory out of it by importing it in Verilog? The said "cells" will have multiple inputs and outputs and consume a lot of wire.
I complied the code for using ADC of lpc2138 in keil4. its hex file is generated but i cant simulate it in proteus. i included header file and all memory locations are correct still it is showing the error " attempt to read undefined register at address E0060010". What is wrong with the simulation?
data_out <= memory; data_out is not a register so you cannot use the above statement. However, you already have instantiated a memory core and are driving data-out with it. You cannot drive data_out in two places. The quoted statement, and in fact the whole always block, are made useless by the presence of the memory
Hi I need help. I'm writing Pipeline mips code in verilog. I don't know how can initialize? in instruction memory and data memory and register file. I attached the file. can you help me pleeeeeeeezzzzzzzzzzzz?
I did not find any tutorial regarding PEIE bit of INTCON register. ... Could you please clarify this thing? Hi; You are right, it is not as easy to find a proper clarifying for the PEIE bit (almost nothing in the datasheet). Look at this site: PIC
How to get these memory compilers? one easy solution is to check ARM website. Artisans(currently ARM) memory compilers can be download by their free library program. Since u need a memory to talk with ur processor, check Artisan library, i think they have register file compiler which could be more suited to (...)
Hi, I want to replace those small SRAM/register file compiled by memory compiler with standard logic (DFF). Could you help to provide some references? Thanks a lot. Best Regards, Newcpu
Hi all, I want to test memories for manufacturing defects. For that I am using MBIST Architect tool from mentor graphics which will insert controller and do the testing. But what my doubt is if I have lot of memories of different types(single port,dual port and two port register file) and of different sizes( data and address), How the tool will
The first point to consider is, how the data is actually organized. It's not clear to me, if you already thought about this problem. If we assume a FPGA internal memory, the solution options are quite different from a register file. But a register file would already require a considerable amount of FPGA (...)
Hi all, I have a very simple memory-mapped AMBA slave module that consists of two registers from and to which can be read or written. I execute the following code to assing some data to REG0 and REG1, however, when checking after execution both registers have a value of 0x00000000... // Create aliases for the register (...)
Hi memory compilers are for: SRAM (single and dual port) ROM RF (register file) FUSE (FUSE Technology) SMIC, TSMC and IBM have their own memory compilers running in Solaris and Newly in Linux.
In microchip it is easily possible to interface with SD crad through FAT32 file system using SPI. For MSP 430, the card (SDHC 4Go) is directly connected to the microcontroller via its USCI (SPI) peripheral. You have to write the basic SD access (register read / write, basically to find if a card is a SDSC or SDHC, page read / write). Follo
hi, everyone there are 2 questions about memory. 1 in general, an off-chip rom or ram is only generated for simulation, and neednot to be synthesized. the question is if u need to synthesize an on-chip ram or register file, or generate it with the help of "memory Compiler" as in question 2. 2 as i know, (...)
This is the thing that I am very confused about. New to assembly language and PIC. :cry: When do you need to select memory bank 0 and when to select memory bank 1? I mean from the register file map, i can see some registers is available on both sides, like INTCON etc. so, how do we know bank 0 or bank 1?
A memory that is initialized during the reset is not a memory but a register...
I believe that sometimes you can use SRAM for implementing register files .. registers files are more of a concept .. try Artisan memory compiler to get more information regarding what ur specifically looking for ..
Yes .. you can use d-flip-flop to build a register file .. But you should listening to what Mr. Lin told ..
Hi, I use smic13 artisanmemory compiler generating single port and dual port register file and use generated verilog lib to make rtl simulation,the simulation process is not I change them with smic18 memory verilog mode,the result is right.Through analyzing,find when at a certain time the data wrote to the (...)
Hi , how can I write VHDL code for a register file that contains two read ports and a write port with seperate address port for each one utilizing the distributed RAM in spartan 3....XST inferred my code as block RAM but I want to use the block RAM for something else .. HELP
So, when someone says, data buffer, does it means, it could be either register(DFF) or RAM? In verilog coding, does it have different coding style to refer to data buffer using registers and to refer to RAM? In verilog, if I declare reg memory If the design goes to synthesis or layout, will it become df