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## Cadence Virtuoso Monte Carlo Problem

Hi everyone, For an LNA design, the inductors used in the design were simulated in a simulation software separate from the spectre simulator used in cadence for the other components (transistors, resistors, capacitors). So we created a n-port file for the inductors in the design and made it point to the S-parameter file generated by the inducto

## [Cadence Virtuoso Schematic] How to connect resistors in series

Well, you could of course just draw out a boring schematic and then symbol-ize it for higher level clarity. Or, you could look more closely at the PDK device's cell options, which may well include both series and parallel options for multistripe resistors.

## [Moved]: impedance matching by using idea_balun or xfmr

I need to match two impedance, for example, one is 5 ohm, and the other is 100 ohm. How can I use the idea_balun or xfmr in cadence analog lib to realize the impedance matching between the two resistors. Thanks.

Hi, In ADE simulation with 2 resistors and 1 nmos, I'm facing error: Circuit has topology errors. Set variable "floatingnodesok" if you want to attempt to run anyway Note: Simulation terminated with errors. There are no floating nodes. How do I set variable "floatingnodesok" ?

I tried to post this message earlier, but it did not seem to go through, so I will try again. I am currently going through a tutorial for Orcad Capture and it is asking that I use a SMDRES footprint for my resistors. I know that surface mount resistors come in various sizes such as 0603, 0805, and 1008. So my question is how would a person know wha

## Opamp input current noise simulation in cadence

I suppose you want to simulate this in a true application, meaning the inputs are controlled by a generator with known output impedance? In this case connect the inputs with noiseless resistors to the required bias voltage. Or subtract the resistors noise, if you can't find noiseless resistors in your libs.

## Impedence Matching for RF circuit at 953MHz

well I you are trying to match the antenna to the circuit, you do NOT want to use and resistors! That would simply make the match better by absorbing the rf power. U need to use capacitors, inductors, transmission lines, or transformers.

ICC is primarily a timing-driven auto-place&route tool for use with standard-cell libraries (sets of pre-made logic gates that make-up a digital design). Everything ICC does is based around this goal - it is not the right tool for custom analog layout of individual transistors, resistors, etc. And for manual design, it's GUI is not designed for han

## extraction problem in assura

I have designed a front-end and now i want to layout it in cadence and post layout it using assura. but there is some problems in extracting extracted file at both of the LNA and mixer , all of transistors have the width fixed to 15u , capacitors to 30fF, all kind of resistors to 5.62k and inductors to a few hundred pH. I manupulated the extrac

## Help: Cadence Layout XL connectivity doing stupid things

I have a layout for series resistors with instance names like: |R1 |R2 |R3 |R4 In my schematic I have four resistors with the nets inbetween named t0, t1, t2. I have the connectivity of these nets well defined in Layout XL. I go to Connectivity->Check->Against Source, and it says there are 0 differences. Then I go to Connectivity->Update->

## problem in post layout simulation and DC operating points in cadence

The attached figure shows the DC operating points of two series resistors rINN_42 and rINN_43. But, as you can see, the currents of these two series resistors are different !!!simulator: spectreAnalysis: DCNote, this is a post layout simulation.What is the problem?Thank you in advance 63892

## How to simulation PLL loop filter noise by cadence spectre

Dear all, How to simulate PLL loop filter noise by cadence spectre? I used 3ord LPF in PLL. As attached figure, dashed lines are resistors noise in LPF and solid lines are output noise after transfer function. Who can help me about LPF noise simulation by cadence spectre. thank you very much. 57617

## error in DRC checking

High-Res perhaps? It is a layer that covers some resistors. You may have placed them too close to each other.

## what is meaning of "ANNOTATE" in circuit simulatio

Yes, that's exactly what annotate means. In cadence, when you run a DC simulation (for example), you can get the node voltages placed on your schematic by selecting Annotate DC Node Voltages; or you can get the DC values for transistors (vth, ids, vdsat, vgs), resistors, etc... by selecting annotate Annotate DC Operating Point... diemilio

## opamp load capacitance for active filter design

Why do you want to chose your capacitors in the filter based on stability? According to me those should be based on noise. I would chose caps and resistors based on noise, then design the opamps accordingly.

## where can i find design rules in cadence?

hi, i m drawing the gilbert mixer layout in cadence, where can i find the design rules? and how to draw layout for passive components resistors, capacitors in cadence? plz halp me out in this,its urgent........ which foundry are you using? what type of cap/res are them?

## Different DRAIN CURRENT values in CADENCE.Which one is true?

Slide on down to the model / macromodel layer, and see if there are any additional elements that you can't see from where you're at. For example there may be leakage resistors, controlled sources, etc. in the macromodel layer. cadence' display texts and terminal currents are mapped to some specific element, but if there's more than one

## high resolution (15 bit) delta sigma ADC simulation problem

I am designing a rather high resolution (>15bit) delta sigma ADC. I have a design that's working in MATLAB and I am trying to build the same thing in cadence using Verilog A modeling. Every component I have now is ideal and in verilog A code, so that means no transistors, no resistors and no capacitors. I am using the function laplace_nd to model m

## who can explain the symbol?

it's not a problem... put labels in your schematic wires wherever there are networks (for example, strings of resistors in parallel) which are equivalent when interchanged, and then also label the same way the layout, then select the option for diva to use labels as references. The msg will disappear then.

## IIP3 of differential pair in Cadence

Hi As I know, resistors are determined by output resistance of previous stage and input resistance of next stage. I'm not sure, mut I think : If you change the resistor, you changed the voltage that is delivered to your circuit, but power is constant yet. so you have different results. regards