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Hi, For the error "incorrect ports" in Calibre LVS hierarchical run, why do some ports appear at the top level and others at the IP level ? What is the basis for them to appear at two levels like this ? Thanks, Aditya
Hello all, I hope someone can help. I have short violations in my low power design. They are happening inside my power domain (i have an internal power net that is routed by Special Route in the power domain), and it happens with Tap cells, Encap cells and Fillers only. Power swicthes and regs are not having shorts. I don't understand why thi
Hi, I am new in this field. I have rtl code of an IP. Now I want to implement wrappers around the i/o ports. Can you please suggest me how to do that? Do i need to write rtl code for the wrappers as well or any other means are available? Thanks in advance.
Hello group, This question is specific to tetramax tool. I need to know if there are tool commands or a TCL script or API in tetramax for the following: Trace the cells and nets from scan-cell clock pin to top PI/driving clock? extending further, I need to get the net paths for all the shift clocks of the scan chain elements traced back t
Hi All, I have some doubt regarding timing arc. What is timing arcs. Is there any hardcore rule that if any port is asynchronous signal then it should have timing arc??
Why leakage current in low Vt cells is high as compare to high Vt cells ?
Regarding Scan Chain, why are we remove scan chain before the placement? and why are we reordering scan chain after the placement?
Hello Guys, I would like to ask for opinion. For some time I am looking for cheap FPGA board with big number of "logic cells" and "DSP blocks". I do not need very high clock frequency and super speed comunication capabilities. I think "bigger" represenstant of Artix-7 or Spartan7 families would be enough. I am experimenting with some kind of vec
Is it possible to combine lead-acid batteries with super-capacitor cells in a DC-DC converter? I have gone through few research articles at IEEE but could not find a simple practical system for EVs. What I need is to maintain the lead-acid battery capacity when high current is drawn (Peukert Law) and, that current should be supplied by the supe
Hi, how power switches are connected to standard cells in the design? how they are connected logically?
I made a cell using copper and aluminum with liquid bleach electrolyte. I used two different meters to measure current. The analog meter highest setting is 250 ma and DMM has 10 amp setting. When using analog meter the current slowly climbs, but the highest I've seen is 200 ma. When I use DMM the current slowly climbs but may go as high as 3 amps.
Hi all, I'm a beginner with Synopsys DC. I synthesized a particular design and later defined and propagated the clocks via the clock ports into the design. Now, I want to trace the clock tree. In particuar, I wish to do the following: 1. Get the cells in the the clock path (I've tried get_cells -hierarchical -filter "is_combinational==t
Hi. A Hoover brand 18V battery pack with 5 cells has three terminals. (+), (-) and (C) How to learn what signal this particular 'C' battery pack contact expects to enter into charging mode ? The pack uses a microcontrolled management circuitry in it. For sure signal is not needed at 'C' to discharge the battery. It powers the load fine with no
Hi, What do the following warnings mean in Calibre ? - WARNING: Cell is referenced but not defined. Empty cell used - WARNING: Cell already exists, will overwrite Thanks, Aditya
For setting driving cells, theres a command -set_driving_cell $LIB $CELLNAME But If i want to set a "load" or loading cell to all output ports, is there a similar function? If not, how do i set some cell (eg. buffer or level shifter) from some timing lib as the load to all output ports? Thanks
Friends, Please review my custom voltage lithium-ion power bank and send me your valuable comments and suggestions. Below is the youtube link. Thanks.
There are on die power gating cells, connect to VDD or VSS. How about their voltage drop? How dose they affect the circuit timing closure? Can anyone give me some clue?
hi , can anyone guide me what we mean by saying a design is a 9 track design or a 12 track design? how do we identify our design in context with previous question? Regards .
Have with few microntrollers. Trying to learn psoc technologies. What psoc is good to start with?. Considering the easiness to start learning the psoc and the low cost what is recommended?.
For doing this, I am using a current sensor that gives me current data(ADC conversion time-532 μs) in continuous conversion mode over I2C(400kHz) and I am using a Raspberry Pi Zero-W to store this data locally. I want to connect the maximum number of sensors on one RPI Zero-W, using bit-banging on different RPI pins, I want to know what is the