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14 Threads found on edaboard.com: Salma Bakr
hi, how can i merge some data needed for my design with the bit file of the design then program the PROM with the resultant file ?? (in Xilinx or Altera) thanks, salma :)
what is soc encounter please, I would like to benefit from the discussion thanks salma:D It's a Cadence tool for place and route Synopsys has Apollo, Astro Magma has Blast Fusion
Is that you Mohammad??? You're networking on facebook with VLSI people exactly like LinkedIn or what??? btw, I heard there's SysDSoft in Alex now :) Good luck :D salma
Can I write PSL properties from a C program??? as if we say it's a HIGH LEVEL type of properties :) thanks alot, salma
it's just spelled like that for protecting trade marks it's q-u-a-r-t-u-s like addn said Now, I got you :D q u @ r t u s But I couldn't find in any book :cry: ep20k
is assume treated exactly as assert in modelsim? assume should normally make a constraint on the inputs, does it do that in modelsim or does it treat the expression as an assert and tries to verify it too? thanks, salma:) Assume in simulation is treated exactly the same as assert. Not sure what Modelsim does,
hey ahmad i'm sorry in being late to reply :) well, i can give u only some info i'm just into some of these tools :( for designcompiler, it's a synthesizer, that uses the specs and constraints of the design to produce a netlist circuit with optimizations such as for area or timing for instance...it's like leonardo spectrum of mentor prim
Hi, i'm reading in a tutorial now and there is something confusing me: a property is as follows: ERROR must not be asserted between an END and the following START ( from one cycle after the END until one cycle after the START ) and it's written as follows in PSL: assert always (END -> next ( START before
what does functionality to I/O mean ??? A "high ratio of functionality to i/o" means that the application has LOTS of internal logic circuitry as compared to its number of i/o's. For example, consider a hypothetical application which performs real time fft conversions and has only the following i/o's: * input: clo
i read in a book about RTL verification this sentence: "we define verifiable RTL as a combination of coding style and methodology techniques that, when used properly, will ensure cooperation and support for multiple EDA tools used during the course of verification" well, i've just started to read about verificatio
try to make an upgrade from the linux CD....not an installation I have tried this but it didn't work. any other solutions Yes, the bootloader wouldn't be updated unless "upgrade" the kernel... May try, boot by your Distro CD1 (The one can boot) mkdir /tmp (There has many ways...) moun
i have a question similar to the above too: how will i program an FPGA that is not on a kit ??? what if i don't need the peripherals on the kit and i wanna employ the FPGA as a chip by its own in a bigger design thanks, salma ok... u mean u hav FPGA chip... not the dev. board... so u need to create ur own
what are cell primitives please...??? thnx salma
what is build gates plz...??? i'm interested to know thnx, salma:D it's Cadence's Synthesis tool .. same as Synopsys's Design Compiler .. Cadence also has RTL Compiler .. which is used for bigger designs or multimillion gate chips .. Synopsys Design Compiler currently has a huge market share .. but Build-G