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466 Threads found on edaboard.com: Sar Sar
hello guys. I just have desined a sar ADC with a 12-bit resolution and 1mhz sampling rate. but i find some problem with it : when i simulated the ENOB with it and i found the enob droped when the frequency of the input sinewave rises. can anyone tell me why this happens and how i can make it solved? thank you all!
The digital scheme with the sar would have to be clocked and then the LDO becomes noisy (or noisier). If the application is a digital load that makes plenty of its own noise, then fine. But many LDO applications are for stuff that needs to be very quiet (like RF, and low jitter clock source PLLs, etc.). You might be able to filter it inside the pa
I am working on a project about sar and I need a SAM Head phantom file to import it into my project.
Hi, I am new to Image Processing domain and want to know difference between SPOT Imagery and sar Imagery. I did some Google before posting this thread but didn't find any useful resource.
Hi All, I am working on 14bit sar ADC with a sampling frequency of 5KS/s. I am supposed to do DNL and INL analysis to get information about missing codes. what I know to do DNL and INL analysis is, apply a super slow ramp so that each code appears at least 10 times. Now my problem is, I have as much as 2^14= 16384 codes and the waveform viewe
Hi All, I am working on 14 bit sar ADC for biomedical applications with a sampling speed of 5KS/s. The DAC architecture is differential and dynamic range is 1vP-P. My circuit level part is completed and now I am heading towards SNR, SNDR, and other spectral analysis for getting ENOB. What I know is to do spectral analysis, apply an input sign
suggest me best process to design simple sar logic block design in cadence virtuoso? please provide some useful online links
im designing double tail comparator for sar adc. Im getting clock signal when input voltage is above reference voltage. How to get low voltage when vin is below reference voltage. Why clock signal is getting triggered in the output signal instead of zero volts. Please reply me..
how to find offset voltage from output waveform of comparator when sinewave signal given as input?
Hi everybody, I designed a coupled-capacitor instrument amplifier, the output of this amplifier will be sampled and converted to digital code by a sar-ADC. As we know, the inputs of sar-ADC VIP, VIN must be the same common voltage level (900mV for Vref=1.8V). Everything is OK when running pre-layout simulation. The (...)
Hi, I'd like to better understand CST default power for WG and for sar calculation. I've used the default power (peak power 1W, or 0.5 RMS), but I got half values compared to a simulation (1W) done with SemCAD. Any suggestions? Many Thanks1
how to observe sar variations with respect to antenna. Is there any PRECATIONS / settings before start simulations of antenna with tissue material. I need sar observations in either CST or HFSS or both softwares.
Many people use sar ADC, some stick to delta-sigma and some like pipelined ADC while designing signal conditioning circuit for SoC or for IoT application Chip. What is your view on this? Which one you will pick and why? There are hell lot of literatu
I am designing a low power 100MHz sar ADC ; but I can not find an accurate differential dynamic comparator for it. Non of the recently published structures work good. Would any one introduce me a proper structure? Thanks
Hi all, I am now designing a 14bit sar ADC, at present, I have designed a prototype with ideal comp and sh. I run transient analysis with stop time 1s (10kS/s sampling rate), around 10000 samples, then I perform FFT analysis in MATLAB with window functions like hanning. However, large spectrum leakage appears and results vary with different wi
I wanna measure my sar ADC's ENOB using Cadence 6.14 can i know the exact steps ?
The sar-12bit may be configured as a DAC but considering the learning curve will have just to make 2 sine waves and the chip capability, I can think of better choices and more suitable applications for the chip when you learn how to use it. A protoboard is not the best for low noise sine waves with long wires. It seems you need to learn how a
125557 Hello I design a 7-bit sar ADC with power requirement maximum of 100nW. now I designed the DAC, and it uses ALONE 101 nW. I need to optimize this power to be range of 20 nW's, any help will be appreciated
im trying to simulate sar in CST MWS. i know i should select power loss/sar in field monitoring to do that. but sar value still not appearing after simulation. so i did open sar examples in CST and create my own phantom because only head phantom available in (...)
i would like to simulate sar in CST. the device is body worn device so sar flat/tank phantom needs to be used. please refer to attached picture for sar flat/tank phantom. how to do sar flat/tank phantom simulation in CST? - - - Updated - - - 123605 (...)
hi all, i would like to do sar simulation using CST. however, i couldnt find human body model in CST2015. they only have face model. does anyone come across this issue before?
hello there. I am working on ADC sar, and focus on ENOB, therefore how to increase ENOB and reduce Power consumption.123033
i need matlab code for evaluating sar (specific absorption rate) using fdtd methode
If you are referring to ESD model, or sar calculation model?
Hi I was looking at some material on recommendations for ADCs and came across the following: "Understanding that the primary real estate consumed on the sar converter chip is analog, it makes sense to connect the power and ground pins on the same planes. While implementing the layout you should connect AGND and DGND to the analog ground
Hello to you all. I am going to use my first sar ADC and I'm not sure if I should put this in the analog section or if its an appropriate topic for this part or not but please move it if it was wrong choice. To the subject at hand, I have a ADC that has a input small-signal-bandwidth of 4MHz while only being able to output 200kSPS max. Appare
Hi, I want to build a sar ADC. I am starting from behavioral level. The comparator is described in VerilogA and the sar logic in Verilog. Can I use spectre simulator for that or do I need another simulator environment for that? thanks a lot for helping
Hello All, I am designing 12 bits asynchronous sar adc 10Mhz sampling frequency and I am done with the layout and it works good with pex but C only (I mean that I extract only capacitor not resistance) but when I tried to extract RC pex the enob became worse about 2 bit less so I am asking what will affect my enob I mean these resistors added by
hello everybody specially alcessia i downloaded your hbm-26--- voxel and i used it in my simulation in cst 2014 mvs . i used it and calculated max sar.now i want to capture the pic to use in my paper but i have major problem.before i genna take pic the voxel disapper . but clearly the voxel is really constant but doesnt show thanks for your
please anyone send me a file of 8-bit adc in matlab
Hi bilalkanj, HFSS supports setting the electric field strength of incident plane waves, yes. It also models sar for different materials.
Have I to calibrate these errors in single sar adc? Comparator offset error, sure, otherwise you'll get a result error corresponding to the offset. The offset error should be < ? LSB , at least during the LSB comparison.
Hello to all respected Members. Wish you to be in good helath. I simulated patch antenna and bend it different textile material for substrate as well patch.... But when I use head model phantom... then my computer slow down and my RAM is 100 utilized.... and some time..give error... also some time it g
hello everybody help me after simulating and sar calculation with CST 2014 mws , when i wanna see my 3d sar distribution result of voxel(.vox) it disappear and i cant see it , vanished . but ineed i know its there , stable, i wanna take pic of 3d results to using in my paper help me, quickly, thanks, rgds,114286[ATT
hello everybody help me after simulating and calculation sar with CST 2014 mws , when i wanna see my 3d result the voxel(.vox) it disappear and i cant see it , vanished . but ineed i know its there , stable, i want to take pic of 3d results to using in my paper help me, quickly, thanks, rgds,:bang::cry: 114104[ATTAC
I am designing sar ADC 3 bit with CMOS organic. I draw circuit by Designwork and simulate with HSPICE. I don't have some parameter for CMOS organic, such as: COX, ECRIT (ESAT), NEFF, VMAX (VMX, VSAT), DERIV, KAPPA, DEL+LD (DLAT, LADT), LDAC, LMLT, LREF, WD, WDAC, WMLT, WREF, XJ, XL (DL, LDEL), XW (DW, WDEL) Please, help me. Thanks very much!
Hello all, I am new to HFSS and I am not familiar with the settings I have to do for sar measurement. I have finished my surface coil design and got the S-parameter now I need to use the frequency of 63.87 MHz as the solution frequency to obtain the sar inside a phantom which I have placed above the radiating coil. I have (...)
Assume the offset is linear/insignificant (with offset-cancellation), the linearity is limited by the matching of the DAC capacitors and the DAC type (binary-/themometer-code). Binary type has fewer switches but larger DNL; both types have the same INL. Hi Guys, Regarding a 10 bit sar adc, using binary capacitance for the D
ADS1174 having ?0,0045 LSB INL Nope. +/- 0.3 LSB, which is still excellent. An INL specification includes an upper limit for DNL, by the way. sar and SD converters have both their specific pros and cons. Obviously SD-ADC have superseded other topologies in the low and medium speed range, you are taking the dataconversion "main ro
Hi, I was looking at several theses on sar ADC and could not find a way to generate required clock signals for sampling the input signal, resetting capacitor and comparator, .... Assuming we have only one clock signal for the sar ADC and we want to generate all required clock pulses internally, how one can generate them (...)
Hi, I wanted to measure SNR in Remcom XFDTD for an RF Coil. But, I don't know how to do it. I am using a xfdtd version 7.2.2.3. Any kind of help is appreciated. Thanks As I understand it XFDTD is used for maximum sar, electric field magnitudes, magnetic flux densities, conduction current magnitudes, o
Hi I am seeing strange problem while simulation sar adc. ADC digital code for signal is as follows. Signal Code 0.5V 0000 0000 0 1000 0000 -0.5V 1111 1111 I would like to invert it so that it start from max code to min code. any suggestions about this ? and one more question is why I am getting this code ?
Hi all, Human body tissues are characterized mainly by three properties Permittivity, Conductivity and loss tangent.. 1)Since the body tissues are dielectric, how it could have conductivity ? For all materials in the material library of HFSS, we have mention these values..(Permittivity, conductivity,loss tangent etc..) 2)How could die
Hi, As frequency increases the penetration depth in tissues decreases, hence the sar must be reduced... In HFSS, sar settings kept the default values in material density and mass of tissue that is 1gm/cm^3 and 1 gm respectively.. what should be the values actually need to be entered? I am simulated with a (...)
On project tree, right click on field monitor and select powerloss/sar mointor I order to for this monitor to register data you will have to define a material that has density values e.g. in the material parameter tab, choose density and insert e.g. Rho: 1200 kg/m^3
Hi, I have seen in some papers that for sar ADCs with 10 to 12 bit resolution, the unit cap was chosen pretty small (ranging from 4fF to 40fF). Though this value satisfies the thermal noise, or matching requirement, but to me there should be a problem with input capacitance of the comparator. For such resolutions, the input pair of the compara
The comparator will be clocked once per bit. Its delay plus the DAC settling time (to 1/2 LSB) and sar logic delay all have to fit into the bit-time window. In your 5MSPS 10 bit ADC that means 50MHz clock rate. You have to do 10 compares w/ logic action, to get the output word and the word comes once per sample (hold). Your conversion time at 5
I have VERY LIMITED experience in sar ADC design. Would you tell me how to tackle the noise and to estimate the resolution of the comparator? Thanks
Hello, everyone! I am studying the specific absorption ratio(sar) in the head from wireless devices. So, I need a human head model, namely a phantom to simulate the realistic situation. I have found a free head model on the web: . But I don't know how to transfer the *.dat format into any other fo
I'm trying to design an ADC in subthreshold region of operation of the MOSFET. It should consume least amount of power. I searched the web and found ADC types - sar, Wilkinson, Dual-slope, ∑-Δ, Flash, etc. I also found a paper entitled "An 8-Bit Single-Ended Ultra-Low-Power sar ADC With a Novel DAC Switching (...)