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466 Threads found on edaboard.com: Sar Sar
hello guys. I just have desined a sar ADC with a 12-bit resolution and 1mhz sampling rate. but i find some problem with it : when i simulated the ENOB with it and i found the enob droped when the frequency of the input sinewave rises. can anyone tell me why this happens and how i can make it solved? thank you all!
The digital scheme with the sar would have to be clocked and then the LDO becomes noisy (or noisier). If the application is a digital load that makes plenty of its own noise, then fine. But many LDO applications are for stuff that needs to be very quiet (like RF, and low jitter clock source PLLs, etc.). You might be able to filter it inside the pa
I am working on a project about sar and I need a SAM Head phantom file to import it into my project.
Hi, I am new to Image Processing domain and want to know difference between SPOT Imagery and sar Imagery. I did some Google before posting this thread but didn't find any useful resource.
Hi All, I am working on 14bit sar ADC with a sampling frequency of 5KS/s. I am supposed to do DNL and INL analysis to get information about missing codes. what I know to do DNL and INL analysis is, apply a super slow ramp so that each code appears at least 10 times. Now my problem is, I have as much as 2^14= 16384 codes and the waveform viewe
Hi All, I am working on 14 bit sar ADC for biomedical applications with a sampling speed of 5KS/s. The DAC architecture is differential and dynamic range is 1vP-P. My circuit level part is completed and now I am heading towards SNR, SNDR, and other spectral analysis for getting ENOB. What I know is to do spectral analysis, apply an input sign
suggest me best process to design simple sar logic block design in cadence virtuoso? please provide some useful online links
im designing double tail comparator for sar adc. Im getting clock signal when input voltage is above reference voltage. How to get low voltage when vin is below reference voltage. Why clock signal is getting triggered in the output signal instead of zero volts. Please reply me..
how to find offset voltage from output waveform of comparator when sinewave signal given as input?
Hi everybody, I designed a coupled-capacitor instrument amplifier, the output of this amplifier will be sampled and converted to digital code by a sar-ADC. As we know, the inputs of sar-ADC VIP, VIN must be the same common voltage level (900mV for Vref=1.8V). Everything is OK when running pre-layout simulation. The (...)
Hi, I'd like to better understand CST default power for WG and for sar calculation. I've used the default power (peak power 1W, or 0.5 RMS), but I got half values compared to a simulation (1W) done with SemCAD. Any suggestions? Many Thanks1
how to observe sar variations with respect to antenna. Is there any PRECATIONS / settings before start simulations of antenna with tissue material. I need sar observations in either CST or HFSS or both softwares.
Many people use sar ADC, some stick to delta-sigma and some like pipelined ADC People decide between ADC techniques based on application parameters like resolution, sample rate, dynamic range, power consumption. i want a quick answer with prose and cones Without some ideas about your application and their requir
I am designing a low power 100MHz sar ADC ; but I can not find an accurate differential dynamic comparator for it. Non of the recently published structures work good. Would any one introduce me a proper structure? Thanks
Hi all, I am now designing a 14bit sar ADC, at present, I have designed a prototype with ideal comp and sh. I run transient analysis with stop time 1s (10kS/s sampling rate), around 10000 samples, then I perform FFT analysis in MATLAB with window functions like hanning. However, large spectrum leakage appears and results vary with different wi
I wanna measure my sar ADC's ENOB using Cadence 6.14 can i know the exact steps ?
The sar-12bit may be configured as a DAC but considering the learning curve will have just to make 2 sine waves and the chip capability, I can think of better choices and more suitable applications for the chip when you learn how to use it. A protoboard is not the best for low noise sine waves with long wires. It seems you need to learn how a
125557 Hello I design a 7-bit sar ADC with power requirement maximum of 100nW. now I designed the DAC, and it uses ALONE 101 nW. I need to optimize this power to be range of 20 nW's, any help will be appreciated
im trying to simulate sar in CST MWS. i know i should select power loss/sar in field monitoring to do that. but sar value still not appearing after simulation. so i did open sar examples in CST and create my own phantom because only head phantom available in (...)
i would like to simulate sar in CST. the device is body worn device so sar flat/tank phantom needs to be used. please refer to attached picture for sar flat/tank phantom. how to do sar flat/tank phantom simulation in CST? - - - Updated - - - 123605 (...)