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14 Threads found on edaboard.com: Sdf Top
is it possible to load the sdf file during simulation ? for example in the testbench initial begin wait(top.i_dut.i_module.signal === 1'b1) $sdf_annotat(...); end
did you use $sdf_annotate("name_of_sdf_file") in testbench or top DUT?
Hi all: I am using Cadence SOC Encounter to extract the post-layout netlist and sdf file. I wrote a testbench in verilog and I added the sdf_annotate command with itput arguments as my sdf file and my top-level instance name. Then during elaboration using the following command in NC-Sim:: ncelab -work worklib (...)
Hello everyone, In my test bench, I have two instances of a top level design, which has two separate blocks (one is RTL (representing analog), one is completely digital (routed with Encounter, and sdf obtained from Primetime STA)). I am not sure how to specify the SCOPE for ncelab. I can specify one instance: SCOPE: test_bench.top_
you should have netlist and sdf filf for ncsim to load !
seems like u r using a student version of modelsim... the timescale directive is different in ur testbench and in ur netlist file. just add the correct timescale in ur top level file tat u simulate(ur tb top) and it should apply to the leaf levels also unless they are described there. make sure u r compiling ur library(say 65nm.v file) along wit
I have two blocks for which I want to annotate delay to top level using Synopsys DC. Can I use propagate_ilm to annotate delay to the top level. How to create_ilm at the block level. Do I need to read in the block level sdf and then create ilm using create_ilm. What about the timing constraints. Do I need to propagate even the (...)
After apply derating factor (ocv) to the block design, sdf is written out to capture the derated cell delays. what is the procedure for annotating the block level sdf to top level in design compiler. What is to be done if i have two such blocks for which derating factor (ocv) is applied and I need to annotate these two block (...)
Hi guys i am trying to load a sdf file for one of the components in my design but i am getting error saying that the instance is not found... i have a top level entity named top_entity and i have a test bench for this as top_entity_tb. top_entity has 2 components called comp1 and comp2 instantiated (...)
$sdf_annotate is a standard function of verilog. all verilog simulator can use it. include nc(xl), vcs & modelsim etc.
JesseKing is right . use write_sdf -version to write out sdf file.
Generally we simulate according to following steps in Modelsim: 1.compile design code & testbench; 2.special the corresponding .sdf file ; 3.excute file which includes "force" section; 4.view waveform. How can I dump waveform to vcd file through up steps directly? And how can I dump waveform to fsdb file directly? Thanks a lot
Please go through manual, aget netlist and make Test bench , apply top level *.sdf file and run.
netlist and sdf file are generated by DC,and using verilog*_xl to simulate them.error happened like this: L1482: sdfA Error: Unable to find source port test.top.sie1.device_addr what can i do it