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133 Threads found on Sdram Data
I did a design using the DLP3000 with its controller. I based my design on the evaluation board just with less sdram (128MB instead of 256MB) and no FPGA. The functionality of the FPGA was to provide video data to the DLP controller. So put a video decoder down with BT656 digital output. The board functionality is controlled by a AVR32 cpu. Ever
I am using DE1-SoC to start bare-metal programming for dual-core Cortex-A9 ARM hard processor, Cyclone V. I'm trying to read data from sdram to FPGA using FPGA-to-HPS sdram Bridge. I configured FPGA-to-HPS sdram interface in qsys to use avalon-MM Read only, 32 width. I exported FPGA-to-HPS sdram (...)
Hi I want to read data from a ddr3 sdram. I'm using vivado. my memory model is M471B2873FHS which is not mentioned in the "xilinx memory interface generator". what should I do? thanks. ( I apologize for my bad English ).
Hi! I want to use a Raspberry Pi to read/write data to DDR3 sdram. JEDEC DDR3 standard: sdram have 240 pins (most are GND, VCC). 64 data
1) Yes, you could use sdram for buffering, but the FIFO is MUCH easier. The FIFO will tell you when it's got data available, when it's empty, when it's full, etc. The sdram won't. 2) I don't know about Quartus, but I don't believe you'll find a UART core with built in FIFO, you'll need two separate cores, but it's not really a big deal. 3) (...)
Hi, I have a Nios system with Qsys components such as Interval timer, UART, sdram and some PIOs. My system specifications are DE0 Nano, Quartus 12.1 sp1, Altera monitor program. Nios II system are interfacing with several VHDL blocks. I am able to read data from FPGA to Nios processor, then transmit this data to Uart component
Hi. I'm trying to use MIG Tool for transferring data on DDR3 SDRM. My component is MT41j64M16JT , with 16bit data bus and DDR3 clock rate of 400MHz. I simulated the example design of MIG to measure transfer rate. It seems to be approximately 1050MB/s for write or read. I want to know is that maximum rate? How can I increase this rate? so
Hello, everybody! I have some misunderstanding about VIH(ac)\VIL(ac) SSTL levels. Timing specification for DDR3-1066 sdram normalized by this levels, for example data setup time tDS is 25ps@AC175 and 90ps@AC135. Which one of all levels I should use in my timing budget calculation? Levels are determined by configuring the controller? or they ar
Hello, i'm working with LPC1788 and i have working LPC1788 development board, in that development board 2 sdram use for LCD data One sdram for D0 to D15 and other for D16 to D31, all control lines and adress lines are common for both sdram. this board work fine. sdram use: 4M X 16 bit X 4 banks Part (...)
Hi all, I am working with a pcb with 4 sdram chips (TSSOP package) .data, address ,control and and clock are connected to all the 4 sdram chips. What is the routing strategy that i should follow.What should be the length of the signals. Thanks in advance
Hi everyBody, I implement an xps system by using the Bus PLB. My IP core is added to the system using Create or Import Peripheral... I want to know how can Microblaze write several data to DDR2 sdram and how the IP core read all the data from this memory, modify it and write it back to DDR2 sdram via the PLB Bus (...)
Hey guys I am working on implementing the algorithm of 2D DCT on Nexy2 from Digilent, which is based on Xilinx Spartan 3E. My main concern is data precision and its implications on the memory. The board has 16MB sdram (which I am planning to use for this calculation) and 16MB Flash Memory (which i'm only planning to use to fetch constant da
Hi, I want to obtain a 128 word burst transfer of data from sdram to BRAM in Nexys 2 board. I have gone throught the nexys 2 reference manual and sample code given at their product page. But that is asynchronous mode read. I want to obtain a burst mode transfer. Also i want to know about the burst transfer to the BRAM from the sdram. I am (...)
hay!! i cant figure out the size of block in this specific DDR in vertex 4, can anyone tell me what is the block size this DDR Vertex 4 contains 64 MB of DDR sdram using two Infineon HYB25D256160BT-7 (or compatible) chips (U4 and U5). Each chip is 16 bits wide and together form a 32-bit data bus capable of running up to 266 MHz.
Hi I have problem about to write sdram. Column address 256, row address 4096, bank 4. When i get image data from camerasensor, the data size is 2592. But sdram's row address is only 256. The image data coming through 2592 to sdram but when i use full page mode, It's need to (...)
Hi I have a problems about how can i get data from camera data to sdram. sdram is HY57V281620ETP-6 and camera's data is 8bits And resolution is 2592x1944. So i want to know what is best way to write to sdram? Pull page? Burst 1,2,4,8? I can't decide about this way. Please help me.
Hello, i'm using Texas Stellaris LM3S9B96. First I am designing the board, so I have to do all the wires between all components and the microcontroller, so when software will be developed everything will be ok. I would like to use a sdram and a CPLD at the same time. The idea is to use address/data bus for both these components, in order to save
hello, i am trying to transfer the data to ddr2 memory using stratix3 board.I am using the ddr2 sdram high performance Mega function.I am using the transcend (1G ddr2 memory) but in memory presets no option for Transcend.Can we use any others standards mentioned in that memory presets?
Can a memory controller support ECC if the sdram used has a width of x16? - - - Updated - - - And is it possible to use 5 of the x16 chips to create a 72 bit width data bus, and still use ECC? Thanks a lot!
hello, I'm doing something about the sdram which controled by XILINX, but I haven't know regard to the sdram. I research something about sdram to you, so can you send some resource to me of sdram or reference code to help me complete my program. I'm great to wait your repeating.